Timer memory map

Based on investigation in https://github.com/soc-hub-fi/headsail-vp/issues/33, we find that HPCs timer is available for HPC CPUs at two locations:

• Via local memory map at 0x5_0000 (0x0 + timer offset)
• Via global memory map at 0x1_FFE5_0000 (external access offset + HPC cfg offset + timer offset)

and for SysCtrl via global memory map at 0xFFE5_0000 (HPC cfg offset + timer offset).