Headsail memory maps

Headsail memory maps

Memory map investigation

• HPC needs the 0x1_0000_0000 "External access", when acting as the initiator, to access locations outside of the HPC subsystem
• HPC as initiator:
  • SDRAM starts at 0x1_0000_0000
    • This has the external bit at 0x1_0000_0000 + SDRAM base at 0x0
  • SDRAM len is 0x7000_0000
  • HPC internal configurations are available via local map in locations 0x0..0x1_0000_0000 and via global map at 0x1_0000_0000 + HPC_config offset.
• SysCtrl as initiator:
  • SDRAM starts at 0x1000_0000
    • The first 0..0x1000_0000 are unavailable on SysCtrl due to legacy memory map.
    • HPC configurations are available via global map at HPC_config
  • SDRAM len (truncated) is 0x6000_0000

SysCtrl internals

We noticed that SysCtrl also has some peculiarities with regard to its memory map. Example: SysCtrl private bank.

• When SysCtrl is the initiator, it uses the "Internal Address Map" (0x1c00_0000)
• When anything but HPC is the initiator, the "External Address Map" is to be used (0xff94_2000)
• When HPC is the initiator, we use both externals at the same time, i.e. SysCtrl external memory map + HPC external access bit (0x1_ff94_2000).

Internal Excel describing the internal & external memory maps.

Implementation on Renode (hardware view)

• common.repl

  sdram_truncated: Memory @ {
    sysbus new Bus.BusPointRegistration { address: 0x1000_0000; cpu: cpu_sysctrl };
    sysbus new Bus.BusPointRegistration { address: 0x1_1000_0000; cpu: cpu_hpc0, cpu_hpc1, cpu_hpc2, cpu_hpc3 };
    }
    size: 0x6000_0000
  

• hpc.repl

  // HPC-only visible part of the SDRAM
  sdram_hpc: Memory @ {
    sysbus new Bus.BusPointRegistration { address: 0x1_0000_0000; cpu: cpu_hpc0, cpu_hpc1, cpu_hpc2, cpu_hpc3 };
    }
    size: 0x1000_0000
  

Impl in link script (software view)

// hpc-sdram.ld
MEMORY {
  SDRAM : ORIGIN = 0x1_0000_0000, LENGTH = 0x7000_0000 
}

// sysctrl-sdram.ld
MEMORY {
  SDRAM : ORIGIN = 0x1000_0000, LENGTH = 0x6000_0000 
}