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@soc-hub-fi

SoC Hub FI

SoC Hub unofficial. Public repositories related to research projects. If you'd like to create a repository remote, contact one of the holders of the Owner role.

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  1. Marian Marian Public

    Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions

    SystemVerilog 9 1

  2. AnTiQ AnTiQ Public

    A hardware priority queue with constant response time written in SystemVerilog.

    SystemVerilog 2 1

  3. Atalanta Atalanta Public

    Tcl 2 1

  4. ReImA ReImA Public

    A Reconfigurable Image Acqusition and Prosessing Subsystem in SystemVerilog.

    SystemVerilog 2

  5. soc-hub-hal soc-hub-hal Public

    (Placeholder) Experimental Rust Hardware Abstraction Layers (HALs) for Ballast RISC-V MPSoC

    1

  6. rt-ibex rt-ibex Public

    Real-time optimized version of Ibex

    SystemVerilog 1 2

Repositories

Showing 10 of 15 repositories
  • Atalanta Public
    soc-hub-fi/Atalanta’s past year of commit activity
    Tcl 2 Apache-2.0 1 4 0 Updated Feb 4, 2025
  • rt-ibex Public

    Real-time optimized version of Ibex

    soc-hub-fi/rt-ibex’s past year of commit activity
    SystemVerilog 1 Apache-2.0 2 0 0 Updated Jan 29, 2025
  • headsail-vp Public

    Headsail — Virtual Platform

    soc-hub-fi/headsail-vp’s past year of commit activity
    Python 0 3 7 3 Updated Dec 16, 2024
  • headsail-tvm Public
    soc-hub-fi/headsail-tvm’s past year of commit activity
    Python 1 Apache-2.0 0 0 0 Updated Nov 29, 2024
  • headsail-riscv-rs Public Forked from rust-embedded/riscv

    Low level access to RISC-V processors (Rust)

    soc-hub-fi/headsail-riscv-rs’s past year of commit activity
    Rust 0 174 0 0 Updated Nov 9, 2024
  • ReImA Public

    A Reconfigurable Image Acqusition and Prosessing Subsystem in SystemVerilog.

    soc-hub-fi/ReImA’s past year of commit activity
    SystemVerilog 2 Apache-2.0 0 0 0 Updated Oct 15, 2024
  • Marian Public

    Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions

    soc-hub-fi/Marian’s past year of commit activity
    SystemVerilog 9 1 0 0 Updated Sep 18, 2024
  • ballast-pac Public

    Rust peripheral access crate for Ballast MPSoC

    soc-hub-fi/ballast-pac’s past year of commit activity
    Rust 0 MIT 1 4 0 Updated Sep 18, 2024
  • keelhaul Public

    Generate executable memory-mapped I/O verification test cases from IP-XACT or CMSIS-SVD files.

    soc-hub-fi/keelhaul’s past year of commit activity
    Rust 0 Apache-2.0 0 5 0 Updated Sep 2, 2024
  • headsail-pac Public

    Memory maps for Headsail MPSoC.

    soc-hub-fi/headsail-pac’s past year of commit activity
    Rust 0 0 0 0 Updated Aug 25, 2024
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