Verilog: {} and {{}} do not need parentheses
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src/verilog/expr2verilog_class.h
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| // Follows Table 11-2 in IEEE 1800-2017. | ||
| // | ||
| // We deviate from the table for the precedence of concatenation | ||
| // and replication, which act like parenteses. |
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| // and replication, which act like parenteses. | |
| // and replication, which act like parentheses. |
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This changes the precedence of concatenation and replication when generating Verilog from expressions such that no additional parentheses are generated.
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Verilog: `{}` and `{{}}` do not need parentheses
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This changes the precedence of concatenation and replication when generating Verilog from expressions such that no additional parentheses are generated.