Verilog: remove verilog_modulet #641
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kroening
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tautschnig
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src/verilog/verilog_parse_tree.cpp
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| verilog_module_sourcet new_module; | ||
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| new_module.name=name.id(); | ||
| new_module.parameter_port_list.swap(parameter_port_list); | ||
| new_module.ports.swap(ports); | ||
| new_module.location=((const exprt &)module_keyword).source_location(); | ||
| new_module.module_items.swap(module_items); | ||
| new_module.base_name(name.id()); |
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Could verilog_module_sourcet be altered so that it at least requires a base name upon construction?
This removes one of the four representations for Verilog modules.
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Verilog: remove verilog_modulet
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This removes one of the four representations for Verilog modules.