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Merge pull request #641 from diffblue/remove_verilog_modulet
Verilog: remove verilog_modulet
2 parents 5c8e134 + c76c90b commit 7491a72

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8 files changed

+61
-173
lines changed

8 files changed

+61
-173
lines changed

src/verilog/Makefile

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,6 @@ SRC = aval_bval_encoding.cpp \
88
verilog_interpreter.cpp \
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verilog_language.cpp \
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verilog_lex.yy.cpp \
11-
verilog_module.cpp \
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verilog_parameterize_module.cpp \
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verilog_parse_tree.cpp \
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verilog_parser.cpp \

src/verilog/verilog_expr.cpp

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,8 @@ Author: Daniel Kroening, [email protected]
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1111
#include <util/prefix.h>
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13+
#include "verilog_typecheck_base.h"
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1315
typet verilog_declaratort::merged_type(const typet &declaration_type) const
1416
{
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typet result = type();
@@ -56,3 +58,40 @@ void verilog_module_sourcet::show(std::ostream &out) const
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out << '\n';
5860
}
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62+
static void submodules_rec(
63+
const verilog_module_itemt &module_item,
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std::vector<irep_idt> &dest)
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{
66+
if(module_item.id() == ID_inst)
67+
{
68+
dest.push_back(
69+
verilog_module_symbol(to_verilog_inst(module_item).get_module()));
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}
71+
else if(module_item.id() == ID_generate_block)
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{
73+
for(auto &sub_item : to_verilog_generate_block(module_item).module_items())
74+
submodules_rec(sub_item, dest);
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}
76+
else if(module_item.id() == ID_generate_if)
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{
78+
auto &generate_if = to_verilog_generate_if(module_item);
79+
submodules_rec(generate_if.then_case(), dest);
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if(generate_if.has_else_case())
81+
submodules_rec(generate_if.else_case(), dest);
82+
}
83+
else if(module_item.id() == ID_generate_for)
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{
85+
submodules_rec(to_verilog_generate_for(module_item).body(), dest);
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}
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}
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std::vector<irep_idt> verilog_module_sourcet::submodules() const
90+
{
91+
std::vector<irep_idt> result;
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93+
for(auto &item : module_items())
94+
submodules_rec(item, result);
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return result;
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}

src/verilog/verilog_expr.h

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1893,6 +1893,13 @@ to_verilog_assume_statement(verilog_statementt &statement)
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class verilog_module_sourcet : public irept
18941894
{
18951895
public:
1896+
verilog_module_sourcet() = default;
1897+
1898+
explicit verilog_module_sourcet(irep_idt _base_name)
1899+
{
1900+
base_name(_base_name);
1901+
}
1902+
18961903
irep_idt base_name() const
18971904
{
18981905
return get(ID_base_name);
@@ -1946,6 +1953,10 @@ class verilog_module_sourcet : public irept
19461953
}
19471954

19481955
void show(std::ostream &) const;
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// The identifiers of the submodules
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// (not: the identifiers of the instances)
1959+
std::vector<irep_idt> submodules() const;
19491960
};
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19511962
inline const verilog_module_sourcet &to_verilog_module_source(const irept &irep)

src/verilog/verilog_language.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,7 @@ void verilog_languaget::dependencies(
138138

139139
const auto &module = (it->second)->verilog_module;
140140

141-
for(auto &identifier : submodules(module))
141+
for(auto &identifier : module.submodules())
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module_set.insert(id2string(identifier));
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}
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}

src/verilog/verilog_module.cpp

Lines changed: 0 additions & 113 deletions
This file was deleted.

src/verilog/verilog_module.h

Lines changed: 0 additions & 48 deletions
This file was deleted.

src/verilog/verilog_parse_tree.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -35,18 +35,18 @@ void verilog_parse_treet::create_module(
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ports.get_sub().front().is_nil())
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ports.clear();
3737

38-
verilog_modulet new_module;
38+
verilog_module_sourcet new_module{name.id()};
3939

40-
new_module.name=name.id();
41-
new_module.parameter_port_list.swap(parameter_port_list);
42-
new_module.ports.swap(ports);
43-
new_module.location=((const exprt &)module_keyword).source_location();
44-
new_module.module_items.swap(module_items);
40+
new_module.add(ID_parameter_port_list) = std::move(parameter_port_list);
41+
new_module.add(ID_ports) = std::move(ports);
42+
new_module.add_source_location() =
43+
((const exprt &)module_keyword).source_location();
44+
new_module.add(ID_module_items) = std::move(module_items);
4545

46-
items.back().verilog_module = new_module.to_irep();
46+
items.back().verilog_module = std::move(new_module);
4747

48-
// add to module map
49-
module_map[new_module.name]=--items.end();
48+
// add to module map
49+
module_map[name.id()] = --items.end();
5050
}
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5252
/*******************************************************************\

src/verilog/verilog_parse_tree.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ Author: Daniel Kroening, [email protected]
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1212
#include <util/string_hash.h>
1313

14-
#include "verilog_module.h"
14+
#include "verilog_expr.h"
1515
#include "verilog_standard.h"
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1717
#include <list>

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