Skip to content

Conversation

smalae
Copy link
Contributor

@smalae smalae commented Aug 11, 2025

wiseconnect: Drop RSI_DEBUG, USART, UDMA, and SAI src files

Copy link
Collaborator

@jerome-pouiller jerome-pouiller left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Ideally, wiseconnect: Patch for sli_si91x_clock_manager.c should contains Upstream-status:. I believe this patch can be applied as-is. So Upstream-status: pending seems the right status.

Dropped RSI_DEBUG, USART, UDMA, and SAI files in import_wiseconnect.py

Signed-off-by: Sai Santhosh Malae <[email protected]>
Origin: Silicon Labs WiseConnect SDK
License: Zlib
URL: https://github.com/siliconlabs/wiseconnect
Commit: 2d79a2763b6ef004edb3c643f21dfb88e32cf4b9
Version: v3.5.0
Purpose: Removed the above file to address the issue wrt
kernel.footprints when pm is enabled.

Signed-off-by: Sai Santhosh Malae <[email protected]>
Upstream-Status: Pending
guard DEBUGINIT() in sli_si91x_clock_manager.c

Signed-off-by: Sai Santhosh Malae <[email protected]>
@smalae smalae force-pushed the drop-unwanted-cmsis-files branch from a66e361 to 51f0a82 Compare September 16, 2025 15:21
@jerome-pouiller jerome-pouiller merged commit edbd418 into zephyrproject-rtos:main Sep 18, 2025
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants