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Integration with riscV core
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@rayanmst
rayanmst committed Sep 12, 2021
1 parent 022f19b commit bd84352
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Showing 25 changed files with 2,648 additions and 120 deletions.
2 changes: 2 additions & 0 deletions memory/iodatabusmux.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ entity iodatabusmux is
ddata_r_adc : in std_logic_vector(31 downto 0);
ddata_r_i2c : in std_logic_vector(31 downto 0);
ddata_r_timer : in std_logic_vector(31 downto 0);
ddata_r_stepmot : in std_logic_vector(31 downto 0);

-- Mux
ddata_r_periph : out std_logic_vector(31 downto 0) --! Connect to data bus mux
Expand All @@ -37,6 +38,7 @@ begin
ddata_r_adc when x"0003",
ddata_r_i2c when x"0004",
ddata_r_timer when x"0005",
ddata_r_stepmot when x"0009",

-- Add new io peripherals here
(others => '0')when others;
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2 changes: 1 addition & 1 deletion memory/iram_quartus.vhd
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Expand Up @@ -65,7 +65,7 @@ BEGIN
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../../software/uart/quartus_main_irq.hex",
init_file => "../../software/step_motor/quartus_main_step_motor.hex",
intended_device_family => "MAX 10",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=1",
lpm_type => "altsyncram",
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Binary file modified peripherals/spi/images/osc_spi_gifs.gif
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Empty file added peripherals/step_motor/sim.s
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164 changes: 90 additions & 74 deletions peripherals/step_motor/stepmotor.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -8,15 +8,33 @@ use ieee.std_logic_1164.all; -- Elementos l
use ieee.numeric_std.all; -- Conversões entre tipos

entity stepmotor is
generic (
--! Chip selec
MY_CHIPSELECT : std_logic_vector(1 downto 0) := "10";
MY_WORD_ADDRESS : unsigned(7 downto 0) := x"10";
DADDRESS_BUS_SIZE : integer := 32
);

port(
clk : in std_logic; -- Clock input
reverse : in std_logic; -- Reverse flag: Changes the rotation direction
rst : in std_logic; -- Reset flag: Changes the step motor to it's initial state

-- Core data bus signals
daddress : in unsigned(DADDRESS_BUS_SIZE-1 downto 0);
ddata_w : in std_logic_vector(31 downto 0);
ddata_r : out std_logic_vector(31 downto 0);
d_we : in std_logic;
d_rd : in std_logic;
dcsel : in std_logic_vector(1 downto 0); --! Chip select
-- ToDo: Module should mask bytes (Word, half word and byte access)
dmask : in std_logic_vector(3 downto 0); --! Byte enable mask

-- hardware input/output signals
reverse : in std_logic; -- Reverse flag: Changes the rotation direction
stop : in std_logic; -- Stop flag: Stops the motor in it's actual position
ena : in std_logic; -- Enable flag: Permits motor control
half_full : in std_logic; -- Half or full step flag: Alternate the steps size
in1, in2, in3, in4 : out std_logic; -- Motor H-bridge control inputs
speed : in unsigned(2 downto 0) -- Defines the motor speed, in a range from 1 to 8
speed : in unsigned(2 downto 0); -- Defines the motor speed, in a range from 1 to 8
in1, in2, in3, in4 : out std_logic -- Motor H-bridge control inputs
);

end entity stepmotor;
Expand Down Expand Up @@ -44,83 +62,81 @@ begin
cntr <= cntr + 1;
end if;
end process rotate;
rot <= cntr(to_integer(speed));
rot <= cntr(7-to_integer(speed));

mealy : process(rot, rst)
begin
if rst = '1' then
state <= A;
end if;
if rising_edge(rot) then
if ena = '1' then
if stop = '0' then
case state is
when A =>
if reverse = '1' and half_full = '0' then
state <= DA;
elsif reverse = '0' and half_full = '0' then
state <= AB;
elsif reverse = '1' and half_full = '1' then
state <= D;
else
state <= B;
end if;
when AB =>
if reverse = '1' then
state <= A;
else
state <= B;
end if;
when B =>
if reverse = '1' and half_full = '0' then
state <= AB;
elsif reverse = '0' and half_full = '0' then
state <= BC;
elsif reverse = '1' and half_full = '1' then
state <= A;
else
state <= C;
end if;
when BC =>
if reverse = '1' then
state <= B;
else
state <= C;
end if;
when C =>
if reverse = '1' and half_full = '0' then
state <= BC;
elsif reverse = '0' and half_full = '0' then
state <= CD;
elsif reverse = '1' and half_full = '1' then
state <= B;
else
state <= D;
end if;
when CD =>
if reverse = '1' then
state <= C;
else
state <= D;
end if;
when D =>
if reverse = '1' and half_full = '0' then
state <= C;
elsif reverse = '0' and half_full = '0' then
state <= DA;
elsif reverse = '1' and half_full = '1' then
state <= C;
else
state <= A;
end if;
when DA =>
if reverse = '1' then
state <= D;
else
state <= A;
end if;
end case;
end if;
if stop = '0' then
case state is
when A =>
if reverse = '1' and half_full = '0' then
state <= DA;
elsif reverse = '0' and half_full = '0' then
state <= AB;
elsif reverse = '1' and half_full = '1' then
state <= D;
else
state <= B;
end if;
when AB =>
if reverse = '1' then
state <= A;
else
state <= B;
end if;
when B =>
if reverse = '1' and half_full = '0' then
state <= AB;
elsif reverse = '0' and half_full = '0' then
state <= BC;
elsif reverse = '1' and half_full = '1' then
state <= A;
else
state <= C;
end if;
when BC =>
if reverse = '1' then
state <= B;
else
state <= C;
end if;
when C =>
if reverse = '1' and half_full = '0' then
state <= BC;
elsif reverse = '0' and half_full = '0' then
state <= CD;
elsif reverse = '1' and half_full = '1' then
state <= B;
else
state <= D;
end if;
when CD =>
if reverse = '1' then
state <= C;
else
state <= D;
end if;
when D =>
if reverse = '1' and half_full = '0' then
state <= C;
elsif reverse = '0' and half_full = '0' then
state <= DA;
elsif reverse = '1' and half_full = '1' then
state <= C;
else
state <= A;
end if;
when DA =>
if reverse = '1' then
state <= D;
else
state <= A;
end if;
end case;
end if;
end if;
end process mealy;
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9 changes: 0 additions & 9 deletions peripherals/step_motor/tb_stepmotor.vhd → ...erals/step_motor/tb_stepmotor-no_core.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,6 @@ begin
reverse => reverse,
rst => rst,
stop => stop,
ena => ena,
half_full => half_full,
in1 => in1,
in2 => in2,
Expand All @@ -43,14 +42,6 @@ begin
wait for 1 ms;
end process clk0;

en0: process is
begin
ena <= '0';
wait for 6 ms;
ena <= '1';
wait;
end process en0;

speed0: process is
begin
rst <='0';
Expand Down
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