Minor stepmotor fixes and initial testbench

peripherals/step_motor/stepmotor.vhd

@@ -1,11 +1,11 @@
 -------------------------------------------------------------------
--- Name        : stepmotor.vhd
--- Author      : Rayan Martins Steinbach
--- Description : Step motor controller 
+-- Name        : stepmotor.vhd                                   --
+-- Author      : Rayan Martins Steinbach                         --
+-- Description : Step motor controller                           --
 -------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+library ieee;                                           -- Biblioteca padrão
+use ieee.std_logic_1164.all;                            -- Elementos lógicos
+use ieee.numeric_std.all;                               -- Conversões entre tipos
 
 entity stepmotor is
     port(
@@ -24,15 +24,16 @@ end entity stepmotor;
 architecture rtl of stepmotor is
     TYPE state_t is (A, AB, B, BC, C, CD, D, DA);
     signal state : state_t;
-    signal rot, cntr : std_logic;
+    signal rot: std_logic;
     signal outs  : std_logic_vector(3 downto 0);
+    signal cntr : unsigned(7 downto 0);
 begin
     in1 <= outs(0);
     in2 <= outs(1);
     in3 <= outs(2);
     in4 <= outs(3);
-    rot <= cntr(to_integer(speed));
-    
+
+
     rotate: process(clk, rst)
     begin
         if rst = '1' then
@@ -43,14 +44,15 @@ begin
             cntr <= cntr + 1;
         end if;
     end process rotate;
+    rot <= cntr(to_integer(speed));
 
     mealy : process(rot, rst)
     begin
         if rst = '1' then
             state <= A;
         end if;
-        if rising_edge(clk_s) then
-            if en = '1' then
+        if rising_edge(rot) then
+            if ena = '1' then
                 if stop = '0' then
                     case state is
                         when A =>
@@ -125,23 +127,25 @@ begin
 
     moore : process(clk)
     begin
-        case state is
-            when A =>
-                outs <= "1000";
-            when AB =>
-                outs <= "1100";
-            when B =>
-                outs <= "0100";
-            when BC =>
-                outs <= "0110";
-            when C =>
-                outs <= "0010";
-            when CD =>
-                outs <= "0011";
-            when D =>
-                outs <= "0001";
-            when DA =>
-                outs <= "1001";
-        end case;
-    end process mealy;
+        if rising_edge(clk) then
+            case state is
+                when A =>
+                    outs <= "1000";
+                when AB =>
+                    outs <= "1100";
+                when B =>
+                    outs <= "0100";
+                when BC =>
+                    outs <= "0110";
+                when C =>
+                    outs <= "0010";
+                when CD =>
+                    outs <= "0011";
+                when D =>
+                    outs <= "0001";
+                when DA =>
+                    outs <= "1001";
+            end case;
+        end if;
+    end process moore;
 end architecture;

peripherals/step_motor/tb_stepmotor.do

@@ -0,0 +1,28 @@
+vlib workstart
+
+#compila projeto: todos os aquivo. Ordem é importante
+vcom stepmotor.vhd tb_stepmotor.vhd 
+
+#Simula (work é o diretorio, testbench é o nome da entity)
+vsim -t ns work.tb_stepmotor
+
+#Mosta forma de onda
+view wave
+
+#Adiciona ondas específicas
+# -radix: binary, hex, dec
+# -label: nome da forma de onda
+add wave -radix binary   -label clk /clk
+add wave -radix binary   -label reverse /reverse
+add wave -radix binary   -label reset /rst
+add wave -radix binary   -label stop /stop
+add wave -radix binary   -label enable /ena
+add wave -radix binary   -label half_full /half_full
+add wave -radix unsigned -label speed /speed 
+add wave -radix binary   -label output /outputs
+add wave                 -label state /motor0/state
+
+#Simula até 500ms
+run 500ms
+
+wave zoomfull

peripherals/step_motor/tb_stepmotor.vhd

@@ -0,0 +1,93 @@
+--! Bibliotecas !--
+library ieee;                                       --! Biblioteca padrão
+use ieee.std_logic_1164.all;                        --! Elementos lógicos
+use ieee.numeric_std.all;                           --! Conversões entre tipos
+
+entity tb_stepmotor is
+end entity tb_stepmotor;
+
+
+architecture RTL of tb_stepmotor is
+    signal clk, reverse, rst, stop,ena : std_logic;
+    signal half_full : std_logic;
+    signal in1: std_logic;
+    signal in2: std_logic;
+    signal in3: std_logic;
+    signal in4: std_logic;
+    signal speed : unsigned(2 downto 0);
+    signal outputs: std_logic_vector(3 downto 0); -- @suppress "signal outputs is never read"
+begin
+    outputs(0) <= in1; outputs(1) <= in2;
+    outputs(2) <= in3; outputs(3) <= in4;
+
+    motor0: entity work.stepmotor
+        port map(
+            clk       => clk,
+            reverse   => reverse,
+            rst       => rst,
+            stop      => stop,
+            ena       => ena,
+            half_full => half_full,
+            in1       => in1,
+            in2       => in2,
+            in3       => in3,
+            in4       => in4,
+            speed     => speed
+        );
+
+    clk0: process is
+    begin
+        clk <= '0';
+        wait for 1 ms;
+        clk <= '1';
+        wait for 1 ms;
+    end process clk0;
+
+    en0: process is
+    begin
+        ena <= '0';
+        wait for 6 ms;
+        ena <= '1';
+        wait;
+    end process en0;
+
+    speed0: process is
+    begin
+        rst <='0';
+        stop <='0';
+        speed <= to_unsigned(0, speed'length);
+        wait for 140 ms;
+        stop <= '1';
+        wait for 10 ms;
+        stop <= '0';
+        rst <= '1';
+        wait for 2 ms;
+        rst <= '0';
+                for i in 0 to 7 loop
+            speed <= to_unsigned(i, speed'length);
+            wait for 20 ms;
+        end loop;
+        wait;
+    end process speed0;
+
+    hf0: process is
+    begin
+        half_full <= '0';
+        wait for 140 ms;
+        half_full <= '1';
+        wait for 140 ms;
+        half_full <= '0';
+        wait;        
+    end process hf0;
+
+    rev0: process is
+    begin
+        reverse <= '0';
+        wait for 70 ms;
+        reverse <= '1';
+        wait for 140 ms;
+        reverse <= '0';
+        wait;
+    end process rev0; 
+
+end architecture RTL;

peripherals/step_motor/work/_info

@@ -0,0 +1,94 @@
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peripherals/step_motor/work/_vmake

@@ -0,0 +1,4 @@
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peripherals/step_motor/workstart/_info

@@ -0,0 +1,10 @@
+m255
+K4
+z2
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+!i10d 8192
+!i10e 25
+!i10f 100
+cModel Technology
+dC:/Users/rayan/Documents/GitHub/riscv-multicycle/peripherals/step_motor