Adds PULP timer_unit driver for timer0 (#20)

* Adds PULP timer_unit driver for timer0

examples/headsail-bsp/Cargo.toml

@@ -18,6 +18,7 @@ hpc = []
 sysctrl = []
 alloc = ["dep:good_memory_allocator", "hpc"]
 sdram = []
+vp = []
 
 # This is generated by the above options, don't use directly
 rt = ["dep:riscv-rt"]
@@ -29,6 +30,7 @@ riscv = { version = "0.11.1" }
 riscv-peripheral = { version = "0.1.0", optional = true }
 riscv-pac = { version = "0.1.1", optional = true }
 good_memory_allocator = { version = "0.1.7", optional = true }
+bit_field = "0.10.2"
 
 [[example]]
 name = "panic"
@@ -49,3 +51,8 @@ required-features = ["rt"]
 name = "alloc"
 path = "examples/alloc.rs"
 required-features = ["alloc", "rt", "sdram"]
+
+[[example]]
+name = "timer0"
+path = "examples/timer0.rs"
+required-features = ["rt"]

examples/headsail-bsp/examples/timer0.rs

@@ -0,0 +1,22 @@
+#![no_std]
+#![no_main]
+
+use headsail_bsp::{rt::entry, sprintln, timer_unit::*};
+
+#[entry]
+fn main() -> ! {
+    sprintln!("Timer0 example");
+    let cnt_start = timer0_get_count();
+    sprintln!("Timer0 counter value at start: {}", cnt_start);
+    sprintln!("Starting timer");
+    timer0_enable();
+    sprintln!("Wasting time...");
+    for _i in 1..1_000_000 {
+        continue;
+    }
+    sprintln!("Stopping timer");
+    timer0_disable();
+    let cnt_stop = timer0_get_count();
+    sprintln!("Timer0 counter value at stop: {}", cnt_stop);
+    loop {}
+}

examples/headsail-bsp/src/lib.rs

@@ -3,6 +3,7 @@
 
 pub mod sprintln;
 pub mod uart;
+pub mod timer_unit;
 
 #[cfg(feature = "hpc")]
 pub use hpc::*;

examples/headsail-bsp/src/mmap.rs

@@ -1 +1,2 @@
 pub(crate) const UART0_ADDR: usize = 0xFFF00000;
+pub(crate) const TIMER0_ADDR: usize = 0x5_0000;

examples/headsail-bsp/src/timer_unit.rs

@@ -0,0 +1,56 @@
+/**
+ * Date: 6/5/2024
+ * Author: Andreas Stergiopoulos ([email protected])
+ *
+ * This is the driver for the PULP timer unit. This driver is to
+ * be used in the VIRTUAL PROTOTYPE ONLY.
+ *
+ * Documentation: https://github.com/pulp-platform/timer_unit/tree/master
+ */
+use crate::{mmap::TIMER0_ADDR, read_u32, write_u32};
+
+use bit_field::BitField;
+
+const TIMER0_CTRL_REG_OFFSET: usize = 0x0;
+const TIMER0_COUNTER_REG_OFFSET: usize = 0x8;
+const TIMER0_ENABLE_BIT: usize = 0b0;
+
+/**
+ * Enables the timer (starts counting).
+ */
+#[inline]
+pub fn timer0_enable() {
+    // Read register
+    let mut reg = read_u32(TIMER0_ADDR + TIMER0_CTRL_REG_OFFSET);
+    // Make enable bit 1
+    reg.set_bit(TIMER0_ENABLE_BIT, true);
+    // Write register back
+    write_u32(TIMER0_ADDR + TIMER0_CTRL_REG_OFFSET, reg);
+}
+
+/**
+ * Disables the timer (stops counting).
+ */
+#[inline]
+pub fn timer0_disable() {
+    // Read register
+    let mut reg = read_u32(TIMER0_ADDR + TIMER0_CTRL_REG_OFFSET);
+    // Write 0 to bit 0 but leave all other bits untouched
+    reg.set_bit(TIMER0_ENABLE_BIT as usize, false);
+    // Write register back
+    write_u32(TIMER0_ADDR + TIMER0_CTRL_REG_OFFSET, reg);
+}
+
+/**
+ * Returns the timer counter (tick value).
+ */
+#[inline]
+pub fn timer0_get_count() -> u32 {
+    return read_u32(TIMER0_ADDR + TIMER0_COUNTER_REG_OFFSET);
+}
+
+#[inline]
+#[cfg(debug_assertions)]
+pub fn timer0_get_ctrl_reg() -> u32 {
+    return read_u32(TIMER0_ADDR + TIMER0_CTRL_REG_OFFSET);
+}