Fixed issues similar to these found on code review #20

soc-hub-fi · May 10, 2024 · 83c995c · 83c995c
1 parent 19fadae
commit 83c995c
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Showing 2 changed files with 5 additions and 10 deletions.
diff --git a/examples/headsail-bsp/src/apb_timer.rs b/examples/headsail-bsp/src/apb_timer.rs
@@ -8,13 +8,12 @@
  */
 use crate::{mmap::TIMER0_ADDR, read_u32, write_u32};
 
-extern crate bit_field;
 use bit_field::BitField;
 
 const TIMER0_COUNTER_REG_OFFSET: usize = 0x0;
 const TIMER0_CTRL_REG_OFFSET: usize = 0x4;
 const TIMER0_CMP_REG_OFFSET: usize = 0x8;
-const TIMER0_ENABLE_BIT: u32 = 0b0;
+const TIMER0_ENABLE_BIT: usize = 0b0;
 
 /**
  * Enables the timer (starts counting).
@@ -24,9 +23,9 @@ pub fn timer0_enable() {
     // Read register
     let mut reg = read_u32(TIMER0_ADDR + TIMER0_CTRL_REG_OFFSET);
     // Make enable bit 1
-    reg.set_bit(TIMER0_ENABLE_BIT as usize, true);
+    reg.set_bit(TIMER0_ENABLE_BIT, true);
     // Write register back
-    write_u32(TIMER0_ADDR + TIMER0_CTRL_REG_OFFSET, reg as u32);
+    write_u32(TIMER0_ADDR + TIMER0_CTRL_REG_OFFSET, reg);
 }
 
 /**
@@ -37,9 +36,9 @@ pub fn timer0_disable() {
     // Read register
     let mut reg = read_u32(TIMER0_ADDR + TIMER0_CTRL_REG_OFFSET);
     // Write 0 to bit 0 but leave all other bits untouched
-    reg.set_bit(TIMER0_ENABLE_BIT as usize, false);
+    reg.set_bit(TIMER0_ENABLE_BIT, false);
     // Write register back
-    write_u32(TIMER0_ADDR + TIMER0_CTRL_REG_OFFSET, reg as u32);
+    write_u32(TIMER0_ADDR + TIMER0_CTRL_REG_OFFSET, reg);
 }
 
 /**

diff --git a/examples/headsail-bsp/src/lib.rs b/examples/headsail-bsp/src/lib.rs
@@ -3,9 +3,6 @@
 
 pub mod sprintln;
 pub mod uart;
-<<<<<<< HEAD
-pub mod timer_unit;
-=======
 pub mod timer {
     #[cfg(not(feature = "vp"))]
     pub use crate::apb_timer::*;
@@ -15,7 +12,6 @@ pub mod timer {
 
 mod apb_timer;
 mod timer_unit;
->>>>>>> Fixes formatting
 
 #[cfg(feature = "hpc")]
 pub use hpc::*;