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    15 repositories

    • Atalanta

      Public
      Tcl
      •
      Apache License 2.0
      •2•2•4•0•Updated Feb 11, 2025Feb 11, 2025

    • rt-ibex

      Public
      Real-time optimized version of Ibex
      SystemVerilog
      •
      Apache License 2.0
      •2•1•0•0•Updated Jan 29, 2025Jan 29, 2025

    • headsail-vp

      Public
      Headsail — Virtual Platform
      Python
      •3•0•7•3•Updated Dec 16, 2024Dec 16, 2024

    • headsail-tvm

      Public
      Python
      •
      Apache License 2.0
      •0•1•0•0•Updated Nov 29, 2024Nov 29, 2024

    • headsail-riscv-rs

      Public
      Low level access to RISC-V processors (Rust)
      Rust
      •169•0•0•0•Updated Nov 9, 2024Nov 9, 2024

    • ReImA

      Public
      A Reconfigurable Image Acqusition and Prosessing Subsystem in SystemVerilog.
      asicfpgacamerainterfaceimage-processingsystemverilogmipicsi-2-camerareconfigurable
      SystemVerilog
      •
      Apache License 2.0
      •0•2•0•0•Updated Oct 15, 2024Oct 15, 2024

    • Marian

      Public
      Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions
      SystemVerilog
      •1•9•0•0•Updated Sep 18, 2024Sep 18, 2024

    • ballast-pac

      Public
      Rust peripheral access crate for Ballast MPSoC
      Rust
      •
      MIT License
      •1•0•4•0•Updated Sep 18, 2024Sep 18, 2024

    • keelhaul

      Public
      Generate executable memory-mapped I/O verification test cases from IP-XACT or CMSIS-SVD files.
      Rust
      •
      Apache License 2.0
      •0•0•5•0•Updated Sep 2, 2024Sep 2, 2024

    • headsail-pac

      Public
      Memory maps for Headsail MPSoC.
      Rust
      •0•0•0•0•Updated Aug 25, 2024Aug 25, 2024

    • rust-rv32emc-docker

      Public
      podman/Docker container with Rust support for rv32emc-unknown-none-elf
      Dockerfile
      •
      MIT License
      •1•0•3•1•Updated Aug 12, 2024Aug 12, 2024

    • AnTiQ

      Public
      A hardware priority queue with constant response time written in SystemVerilog.
      SystemVerilog
      •
      Apache License 2.0
      •1•2•0•0•Updated May 29, 2024May 29, 2024

    • pulpissimo-riscv

      Public
      Low level access to RISC-V processors. Fork of rust-embedded/riscv for PULPissimo based microcontrollers and SoCs.
      Rust
      •169•0•0•0•Updated Jan 31, 2024Jan 31, 2024

    • music

      Public
      High-level model of MUSIC algorithm
      C
      •
      Apache License 2.0
      •0•0•0•0•Updated Jan 24, 2024Jan 24, 2024

    • soc-hub-hal

      Public
      (Placeholder) Experimental Rust Hardware Abstraction Layers (HALs) for Ballast RISC-V MPSoC
      MIT License
      •0•1•0•0•Updated May 21, 2022May 21, 2022