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[HW] Add support for single lane configuration #194

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d960af8
[hardware] Changes for single lane configuration support
sharafat-10xEngineers Dec 9, 2022
cc09801
[hardware] hardware change for single lane.
sharafat-10xEngineers Dec 12, 2022
ef1a1e4
[hardware] Update hardware for single lane.
sharafat-10xEngineers Dec 13, 2022
d43e617
[hardware] updated hardware for vfirst single lane
sharafat-10xEngineers Dec 13, 2022
c042f1b
[hardware] Handle single lane case in addrgen module
sharafat-10xEngineers Dec 13, 2022
75c1b97
[hardware] :bug: fix issue with vfirst hardware
M-Ijaz-10x Dec 13, 2022
5502484
[hardware] Fixed vluxei, vsuxei
sharafat-10xEngineers Dec 15, 2022
074f214
[hardware] vid fixed
sharafat-10xEngineers Dec 19, 2022
e0c7f01
[config] Add the 1_lane configuration
sharafat-10xEngineers Nov 2, 2022
70dfdd9
[config] Update constraint on VLEN(8*64*NrLanes) for all configration
sharafat-10xEngineers Nov 2, 2022
0c18343
[ci] Add the 1_lane configuration to the CI
sharafat-10xEngineers Dec 23, 2022
588578e
[riscv-tests] Updated tests for single lane
sharafat-10xEngineers Dec 23, 2022
5f571d1
[makefile] Update makefile to run the seperate tests for single lane
sharafat-10xEngineers Dec 23, 2022
1734e04
:droplet: Fixed clang-format
sharafat-10xEngineers Dec 28, 2022
9338326
[makefile] Update Makefile
sharafat-10xEngineers Dec 28, 2022
c1c96c1
[config] update vlen to 128 for 1_lane.mk
sharafat-10xEngineers Dec 28, 2022
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14 changes: 7 additions & 7 deletions .github/workflows/ci.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -167,7 +167,7 @@ jobs:
runs-on: ubuntu-20.04
strategy:
matrix:
ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
ara_config: [1_lane, 2_lanes, 4_lanes, 8_lanes, 16_lanes]
needs: tc-llvm
steps:
- uses: actions/checkout@v3
Expand Down Expand Up @@ -198,7 +198,7 @@ jobs:
runs-on: ubuntu-20.04
strategy:
matrix:
ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
ara_config: [1_lane, 2_lanes, 4_lanes, 8_lanes, 16_lanes]
needs: ["tc-llvm", "tc-gcc", "tc-isa-sim"]
steps:
- uses: actions/checkout@v3
Expand Down Expand Up @@ -236,7 +236,7 @@ jobs:
runs-on: ubuntu-20.04
strategy:
matrix:
ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
ara_config: [1_lane, 2_lanes, 4_lanes, 8_lanes, 16_lanes]
needs: ["tc-verilator", "tc-isa-sim"]
steps:
- uses: actions/checkout@v3
Expand Down Expand Up @@ -286,7 +286,7 @@ jobs:
strategy:
matrix:
app: [hello_world, imatmul, fmatmul, iconv2d, fconv2d, fconv3d, jacobi2d, dropout, fft, dwt, exp, softmax, dotproduct, fdotproduct, pathfinder, roi_align]
ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
ara_config: [1_lane, 2_lanes, 4_lanes, 8_lanes, 16_lanes]
needs: ["compile-ara", "compile-apps"]
steps:
- uses: actions/checkout@v3
Expand Down Expand Up @@ -318,7 +318,7 @@ jobs:
runs-on: ubuntu-20.04
strategy:
matrix:
ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
ara_config: [1_lane, 2_lanes, 4_lanes, 8_lanes, 16_lanes]
needs: ["compile-ara", "compile-riscv-tests"]
steps:
- uses: actions/checkout@v3
Expand Down Expand Up @@ -450,7 +450,7 @@ jobs:
runs-on: ubuntu-20.04
strategy:
matrix:
ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
ara_config: [1_lane, 2_lanes, 4_lanes, 8_lanes, 16_lanes]
needs: ["compile-ara", "compile-apps"]
steps:
- uses: actions/checkout@v3
Expand Down Expand Up @@ -668,7 +668,7 @@ jobs:
runs-on: ubuntu-20.04
strategy:
matrix:
ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
ara_config: [1_lane, 2_lanes, 4_lanes, 8_lanes, 16_lanes]
if: always()
needs: ["simulate", "riscv-tests-spike", "riscv-tests-simv"]
steps:
Expand Down
18 changes: 17 additions & 1 deletion apps/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -109,7 +109,15 @@ riscv_tests: $(CVA6_BINARIES) $(ARA_BINARIES)
define rvtest_compile_template
TESTS_$(1) := $(addprefix bin/, $($(addsuffix _ara_tests, $1)))

ifeq ($(nr_lanes), 1)
ifeq ($(1), rv64uv)
bin/$(1)-ara-%: $(TESTS_DIR)/$(1)/1_lane_tests/%.$(2) $(RUNTIME_GCC) linker_script
else
bin/$(1)-ara-%: $(TESTS_DIR)/$(1)/%.$(2) $(RUNTIME_GCC) linker_script
endif
else
bin/$(1)-ara-%: $(TESTS_DIR)/$(1)/%.$(2) $(RUNTIME_GCC) linker_script
endif
mkdir -p bin/
$$(RISCV_CC_GCC) -Iinclude -I$$(TESTS_DIR)/macros/scalar -I$$(TESTS_DIR)/macros/vector $$(RISCV_CCFLAGS_GCC) $$(RISCV_LDFLAGS_GCC) -o $$@ $$< $(RUNTIME_GCC) -T$$(CURDIR)/common/link.ld
$$(RISCV_OBJDUMP) $$(RISCV_OBJDUMP_FLAGS) -D $$@ > [email protected]
Expand All @@ -119,7 +127,15 @@ endef
define rvtest_compile_template_c
TESTS_$(1) := $(addprefix bin/, $($(addsuffix _ara_tests, $1)))

ifeq ($(nr_lanes), 1)
ifeq ($(1), rv64uv)
bin/$(1)-ara-%: $(TESTS_DIR)/$(1)/1_lane_tests/%.$(2) $(RUNTIME_LLVM) linker_script
else
bin/$(1)-ara-%: $(TESTS_DIR)/$(1)/%.$(2) $(RUNTIME_LLVM) linker_script
endif
else
bin/$(1)-ara-%: $(TESTS_DIR)/$(1)/%.$(2) $(RUNTIME_LLVM) linker_script
endif
mkdir -p bin/
$$(RISCV_CC) -Iinclude -I$$(TESTS_DIR)/macros/scalar -I$$(TESTS_DIR)/macros/vector $$(RISCV_CCFLAGS) $$(RISCV_LDFLAGS) -o $$@ $$< $(RUNTIME_LLVM) -T$$(CURDIR)/common/link.ld
$$(RISCV_OBJDUMP) $$(RISCV_OBJDUMP_FLAGS) -D $$@ > [email protected]
Expand Down Expand Up @@ -181,4 +197,4 @@ clean: riscv_tests_spike_clean benchmarks_clean
rm -vf $(RUNTIME_SPIKE)
for app in $(APPS); do cd $(APPS_DIR)/$${app} && rm -f $$(find . -name "*.c.o*" -o -name "*.S.o*") && cd ..; done

.INTERMEDIATE: $(addsuffix /main.c.o,$(APPS))
.INTERMEDIATE: $(addsuffix /main.c.o,$(APPS))
6 changes: 5 additions & 1 deletion apps/common/riscv_tests.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,11 @@ include $(TESTS_DIR)/rv64um/Makefrag
include $(TESTS_DIR)/rv64ua/Makefrag
include $(TESTS_DIR)/rv64uf/Makefrag
include $(TESTS_DIR)/rv64ud/Makefrag
include $(TESTS_DIR)/rv64uv/Makefrag
ifeq ($(nr_lanes), 1)
include $(TESTS_DIR)/rv64uv/1_lane_tests/Makefrag
else
include $(TESTS_DIR)/rv64uv/Makefrag
endif
include $(TESTS_DIR)/rv64si/Makefrag

rv64ui_ara_tests := $(addprefix rv64ui-ara-, $(rv64ui_sc_tests))
Expand Down
178 changes: 178 additions & 0 deletions apps/riscv-tests/isa/rv64uv/1_lane_tests/Makefrag
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Original file line number Diff line number Diff line change
@@ -0,0 +1,178 @@
# Copyright 2021 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
#
# Author: Matheus Cavalcante <[email protected]>
# Basile Bougenot <[email protected]>

rv64uv_sc_tests = vaadd \
vaaddu\
vsadd \
vsaddu \
vsmul \
vssra \
vssrl \
vnclip \
vnclipu \
vadd \
vsub \
vrsub \
vwaddu \
vwsubu \
vwadd \
vwsub \
vsext \
vzext \
vadc \
vmadc \
vsbc \
vmsbc \
vand \
vor \
vxor \
vsll \
vsrl \
vsra \
vnsrl \
vnsra \
vmseq \
vmsne \
vmsltu \
vmslt \
vmsleu \
vmsle \
vmsgtu \
vmsgt \
vminu \
vmin \
vmaxu \
vmax \
vmul \
vmulh \
vmulhu \
vmulhsu \
vdivu \
vdiv \
vremu \
vrem \
vwmul \
vwmulu \
vwmulsu \
vmacc \
vnmsac \
vmadd \
vnmsub \
vwmaccu \
vwmacc \
vwmaccsu \
vwmaccus \
vmerge \
vmv \
vmvxs \
vmvsx \
vfmvfs \
vfmvsf \
vmvnrr \
vredsum \
vredmaxu \
vredmax \
vredminu \
vredmin \
vredand \
vredor \
vredxor \
vwredsumu \
vwredsum \
vfadd \
vfsub \
vfrsub \
vfwadd \
vfwsub \
vfmul \
vfdiv \
vfrdiv \
vfwmul \
vfmacc \
vfnmacc \
vfmsac \
vfnmsac \
vfmadd \
vfnmadd \
vfmsub \
vfnmsub \
vfwmacc \
vfwnmacc \
vfwmsac \
vfwnmsac \
vfsqrt \
vfmin \
vfmax \
vfredusum \
vfredosum \
vfredmin \
vfredmax \
vfwredusum \
vfwredosum \
vfclass \
vfsgnj \
vfsgnjn \
vfsgnjx \
vfmerge \
vfmv \
vmfeq \
vmfne \
vmflt \
vmfle \
vmfgt \
vmfge \
vfcvt \
vfwcvt \
vfncvt \
vmand \
vmnand \
vmandnot \
vmor \
vmnor \
vmornot \
vmxor \
vmxnor \
vslideup \
vslidedown \
vslide1up \
vfslide1up \
vslide1down \
vfslide1down \
vl \
vl1r \
vle1 \
vls \
vluxei \
vs \
vs1r \
vse1 \
vss \
vsuxei \
vsetivli\
vsetvli\
vsetvl\
vmsbf \
vmsof \
vmsif \
viota \
vid \
vcpop \
vfirst \
vle8 \
vse8 \
vle16 \
vse16 \
vle32 \
vse32 \
vle64 \
vse64

#rv64uv_sc_tests = vaadd vaaddu vadc vasub vasubu vcompress vfirst vid viota vl vlff vl_nocheck vlx vmsbf vmsif vmsof vpopc_m vrgather vsadd vsaddu vsetvl vsetivli vsetvli vsmul vssra vssrl vssub vssubu vsux vsx

rv64uv_p_tests = $(addprefix rv64uv-p-, $(rv64uv_sc_tests))

spike_ctests += $(rv64uv_p_tests)
59 changes: 59 additions & 0 deletions apps/riscv-tests/isa/rv64uv/1_lane_tests/vaadd.c
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Original file line number Diff line number Diff line change
@@ -0,0 +1,59 @@
// Copyright 2021 ETH Zurich and University of Bologna.
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51
//
// Author: Matheus Cavalcante <[email protected]>
// Basile Bougenot <[email protected]>

#include "vector_macros.h"

void TEST_CASE1(void) {
set_vxrm(0); // setting vxrm to rnu rounding mode
VSET(4, e8, m1);
VLOAD_8(v1, 1, -2, -3, 4);
VLOAD_8(v2, 1, 2, -3, 3);
__asm__ volatile("vaadd.vv v3, v1, v2" ::);
VCMP_U8(1, v3, 1, 0, -3, 4);
}

void TEST_CASE2(void) {
set_vxrm(1); // setting vxrm to rne rounding mode
VSET(4, e8, m1);
VLOAD_8(v1, 1, -2, -3, 4);
VLOAD_8(v2, 1, 9, -3, 5);
VLOAD_8(v0, 0xA, 0x0, 0x0, 0x0);
VCLEAR(v3);
__asm__ volatile("vaadd.vv v3, v1, v2, v0.t" ::);
VCMP_U8(2, v3, 0, 4, 0, 4);
}

void TEST_CASE3(void) {
set_vxrm(2); // setting vxrm to rdn rounding mode
VSET(4, e32, m1);
VLOAD_32(v1, 1, -2, 3, -4);
const uint32_t scalar = 5;
__asm__ volatile("vaadd.vx v3, v1, %[A]" ::[A] "r"(scalar));
VCMP_U32(3, v3, 3, 1, 4, 0);
}

// Dont use VCLEAR here, it results in a glitch where are values are off by 1
void TEST_CASE4(void) {
set_vxrm(3); // setting vxrm to rod rounding mode
VSET(4, e32, m1);
VLOAD_32(v1, 1, 2, 3, 4);
const uint32_t scalar = 5;
VLOAD_32(v0, 0xA, 0x0, 0x0, 0x0);
VCLEAR(v3);
__asm__ volatile("vaadd.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
VCMP_U32(4, v3, 0, 3, 0, 5);
}

int main(void) {
INIT_CHECK();
enable_vec();
TEST_CASE1();
TEST_CASE2();
TEST_CASE3();
TEST_CASE4();
EXIT_CHECK();
}
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