[CPU][ARM] ARM NEON load/store fix for int8/uint8 #32781
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aobolensk
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Nov 18, 2025
| if (broadcast) { | ||
| utils::load_vector(data.b, data.s, ptr_reg, ptr_offset, broadcast, this); | ||
| } else { | ||
| const size_t lane_count = cpu_isa_traits<isa>::vlen / dst_prc.size(); |
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Does it make sense to move this logic to utils::load_vector? As for me, it seems every time we want to load_vector from anywhere else we actually want to preserve boundaries correctly in case of broadcast == false
aobolensk
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Nov 18, 2025
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BTW, do we need to reflect this fix for store?
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@aobolensk done |
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…fset-safe load/store handling. Updated the i8/u8 path in jit_uni_eltwise_generic<…>::store_vector to use the new helper with proper lane_count, mirroring the load-side fix.
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Implemented an ARM NEON load/store fix so int8/uint8 vectors are read lane‑by‑lane instead of pulling a full 16‑byte block and overrunning buffers. In src/plugins/intel_cpu/src/nodes/kernels/aarch64/jit_uni_eltwise_generic.cpp the i8/u8 branch now uses ld1 on individual byte lanes (with broadcast still using the old helper) and only then performs the sign/zero extends, preventing illegal memory accesses when mixed‑precision eltwise ops hit the JIT.