Fix store

Author: allnes

src/plugins/intel_cpu/src/nodes/kernels/aarch64/jit_uni_eltwise_generic.cpp

@@ -356,32 +356,6 @@ void load_vector(const T1& data_lane,
     }
 }
 
-template <typename T1, typename T2>
-void store_vector(const T1& data_lane,
-                  const T2& data_lanes,
-                  const Xbyak_aarch64::XReg& ptr_reg,
-                  const int64_t offset,
-                  jit_generator* h,
-                  const size_t lane_count = 0) {
-    if (lane_count == 0) {
-        if (offset == 0) {
-            h->st1(data_lanes, ptr(ptr_reg));
-        } else {
-            h->add_imm(h->X_DEFAULT_ADDR, ptr_reg, offset, h->X_TMP_0);
-            h->st1(data_lanes, ptr(h->X_DEFAULT_ADDR));
-        }
-    } else {
-        for (size_t lane = 0; lane < lane_count; ++lane) {
-            const auto lane_offset = offset + static_cast<int64_t>(lane);
-            if (lane_offset == 0) {
-                h->st1(data_lane[static_cast<int>(lane)], ptr(ptr_reg));
-            } else {
-                h->add_imm(h->X_DEFAULT_ADDR, ptr_reg, lane_offset, h->X_TMP_0);
-                h->st1(data_lane[static_cast<int>(lane)], ptr(h->X_DEFAULT_ADDR));
-            }
-        }
-    }
-}
 }  // namespace utils
 
 template <dnnl::impl::cpu::aarch64::cpu_isa_t isa>
@@ -575,7 +549,16 @@ void jit_uni_eltwise_generic<isa>::store_vector(const XReg& ptr,
     case ov::element::i8:
     case ov::element::u8: {
         const size_t lane_count = cpu_isa_traits<isa>::vlen / src_prc.size();
-        utils::store_vector(data.b, data.b, ptr, ptr_offset, this, lane_count);
+        auto data_bytes = data;
+        for (size_t lane = 0; lane < lane_count; ++lane) {
+            const auto lane_offset = ptr_offset + static_cast<int32_t>(lane);
+            if (lane_offset == 0) {
+                st1(data_bytes.b[static_cast<int>(lane)], Xbyak_aarch64::ptr(ptr));
+            } else {
+                add_imm(X_DEFAULT_ADDR, ptr, lane_offset, X_TMP_0);
+                st1(data_bytes.b[static_cast<int>(lane)], Xbyak_aarch64::ptr(X_DEFAULT_ADDR));
+            }
+        }
         break;
     }
     default: {