multiplexer example

.gitignore

@@ -3,3 +3,5 @@
 .settings
 
 *.cf
+
+.library_mapping.xml

mux_4to1.vhd

@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity Multiplexer_4to1 is
+    port (
+        ABCD    : in std_logic_vector(3 downto 0);
+        Sel     : in std_logic_vector(1 downto 0);
+        F       : out std_logic
+    );
+end entity;
+
+architecture Multiplexer_4to1_arch of Multiplexer_4to1 is
+begin
+    Multiplexer4to1 : process(ABCD, Sel)
+    begin
+        case Sel is
+            when "00"       => F <= ABCD(0);
+            when "01"       => F <= ABCD(1);
+            when "10"       => F <= ABCD(2);
+            when "11"       => F <= ABCD(3);
+            when others     => F <= 'X';
+        end case;
+    end process;
+end architecture;
+

mux_4to1_tb.vhd

@@ -0,0 +1,56 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_textio.all;
+
+library STD;
+use STD.textio.all;
+
+entity Multiplexer_4to1Tb is
+end entity;
+
+architecture Multiplexer_4to1Tb_arch of Multiplexer_4to1Tb is
+
+    component Multiplexer_4to1
+    port (
+        ABCD    : in std_logic_vector(3 downto 0);
+        Sel     : in std_logic_vector(1 downto 0);
+        F       : out std_logic
+    );
+    end component;
+
+    signal ABCD_TB : std_logic_vector(3 downto 0);
+    signal Sel_TB  : std_logic_vector(1 downto 0);
+    signal F_TB    : std_logic;
+
+begin
+
+    DUT : Multiplexer_4to1 port map(ABCD => ABCD_TB, Sel => Sel_TB, F => F_TB);
+
+    process
+        file Fin  : TEXT open READ_MODE is "mux_4to1_tests.txt";
+
+        variable current_read_line   : line;
+        variable current_read_field1 : std_logic_vector(0 to 3);
+        variable current_read_field2 : std_logic_vector(0 to 1);
+        variable current_read_field3 : std_logic;
+
+    begin
+        while (not endFile(Fin)) loop
+
+            readline(Fin, current_read_line);
+            read(current_read_line, current_read_field1);
+            read(current_read_line, current_read_field2);
+            read(current_read_line, current_read_field3);
+
+            ABCD_TB <= current_read_field1;
+            Sel_TB  <= current_read_field2;
+            wait for 50 ns;
+
+            assert(F_TB = current_read_field3);
+
+        end loop;
+
+        wait;
+    end process;
+
+end architecture;

mux_4to1_tests.txt

@@ -0,0 +1,20 @@
+1000 00 0
+1000 01 0
+1000 10 0
+1000 11 1
+1101 00 1
+1101 01 0
+1101 10 1
+1101 11 1
+0111 00 1
+0111 01 1
+0111 10 1
+0111 11 0
+1010 00 0
+1010 01 1
+1010 10 0
+1010 11 1
+0101 00 1
+0101 01 0
+0101 10 1
+0101 11 0