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SystemVerilog allows a broad range of items to appear at the compilation unit level. This changes the parse tree to be a list of generic compilation unit items.

SystemVerilog allows a broad range of items to appear at the compilation
unit level.  This changes the parse tree to be a list of generic compilation
unit items.
@kroening kroening force-pushed the verilog_package_itemt branch from 6389e67 to b76612a Compare August 27, 2024 18:26
@kroening kroening marked this pull request as ready for review August 27, 2024 18:30
@tautschnig tautschnig merged commit 77937fe into main Aug 27, 2024
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@tautschnig tautschnig deleted the verilog_package_itemt branch August 27, 2024 18:54
Romy15200 pushed a commit to Romy15200/nws that referenced this pull request Aug 19, 2025
Verilog: parse tree now is a list of generic compilation unit items
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2 participants