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SystemVerilog: grammar for expect property #558

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Merged
merged 1 commit into from
Jun 19, 2024
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This adds parsing/typechecking for SystemVerilog expect property statements.

This adds parsing/typechecking for SystemVerilog expect property statements.
@kroening kroening marked this pull request as ready for review June 18, 2024 21:30
@tautschnig tautschnig merged commit aa87b44 into main Jun 19, 2024
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@tautschnig tautschnig deleted the verilog_expect_property branch June 19, 2024 09:45
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