Merge pull request #239 from diffblue/ports4

Verilog: fix module port binding

Author: tautschnig

regression/verilog/modules/ports4.desc

@@ -0,0 +1,8 @@
+CORE
+ports4.v
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--

regression/verilog/modules/ports4.v

@@ -0,0 +1,13 @@
+module submodule(input [7:0] data);
+
+  always assert p0: data == 123;
+
+endmodule
+
+module main#(parameter MY_PARAMETER = 123)();
+
+  submodule instance(MY_PARAMETER);
+
+  always assert p1: MY_PARAMETER == 123;
+
+endmodule

src/verilog/verilog_synthesis.cpp

@@ -964,8 +964,11 @@ void verilog_synthesist::instantiate_port(
     throw 0;
   }
 
+  auto value_synthesized = synth_expr(value, symbol_statet::SYMBOL);
+
   trans.invar().add_to_operands(equal_exprt(
-    typecast_exprt::conditional_cast(it->second, value.type()), value));
+    typecast_exprt::conditional_cast(it->second, value_synthesized.type()),
+    value_synthesized));
 }
 
 /*******************************************************************\