Verilog: port connection values must be synthesized

This fixes the creation of constraints for module port connections; the
given value expression is now synthesized.

Author: kroening

regression/verilog/modules/ports4.desc

@@ -1,9 +1,8 @@
-KNOWNBUG
+CORE
 ports4.v
 --bound 0
 ^EXIT=0$
 ^SIGNAL=0$
 --
 ^warning: ignoring
 --
-The parameter in the module instance port binding is not expanded.

src/verilog/verilog_synthesis.cpp

@@ -964,8 +964,11 @@ void verilog_synthesist::instantiate_port(
     throw 0;
   }
 
+  auto value_synthesized = synth_expr(value, symbol_statet::SYMBOL);
+
   trans.invar().add_to_operands(equal_exprt(
-    typecast_exprt::conditional_cast(it->second, value.type()), value));
+    typecast_exprt::conditional_cast(it->second, value_synthesized.type()),
+    value_synthesized));
 }
 
 /*******************************************************************\