fix problem wrt iverilog version

bin/runbsc

@@ -91,13 +91,13 @@ case "$CMD" in
 	#Run simulation in Bluesim
 	"$BSC" $ARGS -sim $BPATH "$TOP".bsv
 	"$BSC" $ARGS $BPATH -sim -o "$TB".bexe -e "$TB" "$TB".ba
-	timeout "$TOUT"s ./"$TB".bexe | grep -v "WARNING" > "$SIMOUT"	
+	timeout "$TOUT"s ./"$TB".bexe | grep -v "WARNING" | grep -v "\$finish" > "$SIMOUT"
 	;;
     "s")
 	#Run simulation in Verilog
 	"$BSC" $ARGS $BPATH $VPATH $VSIM -vdir $VDIR -simdir $SDIR -u "$TOP".bsv
 	"$BSC" $ARGS $VPATH $VSIM -verilog -vdir $VDIR -simdir $SDIR -o "$TB".bexe -e "$TB" "$VDIR"/"$TB".v
-	timeout "$TOUT"s ./"$TB".bexe | grep -v "WARNING" > "$SIMOUT"
+	timeout "$TOUT"s ./"$TB".bexe | grep -v "WARNING" | grep -v "\$finish" > "$SIMOUT"
 	;;
     "c")
 	rm -f *.bi *.bo *.ba

src/test/scala/pipedsl/RiscSuite.scala

@@ -27,21 +27,19 @@ class RiscSuite extends AnyFunSuite {
   //For each processor impl
   testFiles.foreach(t => {
     val testBaseName = getTestName(t)
-    if (testBaseName.contains("exn")) {
-      test(testBaseName + " Typecheck") {
-        testTypecheck(testFolder, t)
-      }
-      test(testBaseName + " BSV Compile") {
-        testBlueSpecCompile(testFolder, t, None, Map())
-      }
-      //For each program
-      sims.foreach(s => {
-        val simInputs = getInputMap(s)
-        test(testBaseName + " Simulate " + s) {
-          testBlueSpecSim(testFolder, t, None, simInputs, Some(s + ".simsol"))
-        }
-      })
+    test(testBaseName + " Typecheck") {
+      testTypecheck(testFolder, t)
     }
+    test(testBaseName + " BSV Compile") {
+      testBlueSpecCompile(testFolder, t, None, Map())
+    }
+    //For each program
+    sims.foreach(s => {
+      val simInputs = getInputMap(s)
+      test(testBaseName + " Simulate " + s) {
+        testBlueSpecSim(testFolder, t, None, simInputs, Some(s + ".simsol"))
+      }
+    })
 
   })
 }