further exn change

bscRuntime/libs/BypassRF.v

@@ -1,3 +1,4 @@
+// BypassRF.v
 `ifdef BSV_ASSIGNMENT_DELAY
 `else
  `define BSV_ASSIGNMENT_DELAY

bscRuntime/libs/Ehr.bsv

@@ -1,3 +1,4 @@
+// Ehr.bsv
 
 // Copyright (c) 2017 Massachusetts Institute of Technology
 // 

bscRuntime/libs/Memories.bsv

@@ -1,3 +1,4 @@
+// Memories.bsv
 package Memories;
 
 import GetPut :: *;

bscRuntime/libs/Named.bsv

@@ -1,3 +1,4 @@
+// Named.bsv
 package Named;
 
 import Memories :: *;

bscRuntime/libs/NamedEhr.bsv

@@ -1,3 +1,4 @@
+// NamedEhr.bsv
 package Named;
 
 import RegFile :: *;

bscRuntime/libs/PrioFifo.bsv

@@ -1,3 +1,4 @@
+// PrioFifo.bsv
 package PrioFifo;
 
 import FIFOF :: *;

bscRuntime/libs/Speculation.bsv

@@ -1,3 +1,4 @@
+// Speculation.bsv
 package Speculation;
 
 import Vector :: *;

bscRuntime/libs/nametb.bsv

@@ -1,3 +1,4 @@
+// nametb.bsv
 import Named::*;
 import FIFO::*;
 

bscRuntime/libs/project/build.properties

@@ -0,0 +1 @@
+sbt.version=1.6.2

bscRuntime/libs/tb.bsv

@@ -1,3 +1,4 @@
+// tb.bsv
 import Memories :: *;
 import Connectable :: *;
 

bscRuntime/memories/Ehr.bsv

@@ -1,3 +1,4 @@
+// Ehr.bsv
 
 // Copyright (c) 2017 Massachusetts Institute of Technology
 // 

bscRuntime/memories/Interrupt.bsv

@@ -0,0 +1,35 @@
+package Interrupt;
+
+import FIFOF :: *;
+import Ehr :: *;
+
+interface TimingInterruptController#(numeric type addr);
+    method ActionValue#(Bool) req(Int#(addr) a);
+    method Action ack(Int#(addr) a);
+endinterface
+
+module mkTimingInterruptController(TimingInterruptController#(addr) _unused_);
+
+    Reg#(Bool) status <- mkReg(False);
+    Reg#(UInt#(10)) timer <- mkReg(0);
+    Wire#(Int#(addr)) getAck <- mkWire();
+
+    // rule to update timer and set status to True every 1000 cycle
+    rule updateTimer;
+        timer <= timer + 1;
+        if (timer == 999) begin
+            timer <= 0;
+            status <= True;
+        end
+    endrule
+
+    method ActionValue#(Bool) req(Int#(addr) p);
+        return status;
+    endmethod
+
+    method Action ack(Int#(addr) a);
+        status <= False;
+    endmethod
+endmodule
+
+endpackage

bscRuntime/memories/Locks.bsv

@@ -1,3 +1,4 @@
+// Locks.bsv
 package Locks;
 
 import FIFOF :: *;

bscRuntime/memories/Makefile

@@ -1,5 +1,5 @@
 BSC=bsc -no-show-timestamps -no-show-version --aggressive-conditions
-TOBUILD=Ehr.bo Locks.bo Memories.bo Speculation.bo SpecialQueues.bo
+TOBUILD=Ehr.bo Locks.bo Memories.bo Speculation.bo SpecialQueues.bo Interrupt.bo
 
 ## Default simulator is iverilog
 VSIM = -vsim iverilog

bscRuntime/memories/Memories.bsv

@@ -1,3 +1,4 @@
+// Memories.bsv
 package Memories;
 
 import GetPut :: *;
@@ -331,6 +332,8 @@ module mkAsyncMem(AsyncMem#(addr, elem, MemId#(inflight), n) _unused_)
    Wire#(Tuple3#(Bit#(n), addr, elem)) toMem <- mkWire();
    Wire#(elem) fromMem <- mkWire();
 
+   RWire#(Bool) doClear <- mkRWireSBR();
+
    //this must be at least size 2 to work correctly (safe bet)
    Vector#(inflight, Ehr#(2, elem)) outData <- replicateM( mkEhr(unpack(0)) );
    Vector#(inflight, Ehr#(2, Bool)) valid <- replicateM( mkEhr(False) );
@@ -348,17 +351,24 @@ module mkAsyncMem(AsyncMem#(addr, elem, MemId#(inflight), n) _unused_)
       valid[idx][0] <= True;
    endrule
 
+   (*conflict_free = "freeResp, doClearRule"*)
    (*fire_when_enabled*)
    rule freeResp;
       valid[freeEntry][1] <= False;
    endrule
 
-   method Action clear();
+   (*no_implicit_conditions*)
+   rule doClearRule (doClear.wget() matches tagged Valid.d);
+      //$display("Memory Cleared");
       head <= 0;
       for (Integer i = 0; i < valueOf(inflight); i = i + 1) begin
-	 MemId#(inflight) ent = fromInteger(i);
-	 valid[ent][1] <= False;
+	    MemId#(inflight) ent = fromInteger(i);
+	    valid[ent][1] <= False;
       end
+   endrule
+
+   method Action clear();
+      doClear.wset(True);
    endmethod
 
    method ActionValue#(MemId#(inflight)) req1(addr a, elem b, Bit#(n) wmask) if (okToRequest);

bscRuntime/memories/SpecialQueues.bsv

@@ -1,3 +1,4 @@
+// SpecialQueues.bsv
 package SpecialQueues;
 
 import Ehr :: *;
@@ -57,26 +58,26 @@ module mkNBFIFOF(FIFOF#(dtyp)) provisos (Bits#(dtyp, szdtyp));
    FIFOF#(dtyp) f <- mkFIFOF();
    //allow multiple writes in the same cycle
    RWire#(dtyp) enq_data <- mkRWireSBR();
+   RWire#(Bool) doClear <- mkRWireSBR();
 
-   //Make sure no enq could happen during clear (takes 2 cycles)
-   Reg#(Bool) clearCalled <- mkReg(False);
-
-   rule doClear(clearCalled);
-      f.clear();
-      clearCalled <= False;
-   endrule
-
+   (*conflict_free = "doEnqRule, doClearRule"*)
    (*fire_when_enabled*)
-   rule doEnq (enq_data.wget() matches tagged Valid.d);
+   rule doEnqRule (enq_data.wget() matches tagged Valid.d);
       f.enq(d);
    endrule
 
+   //reset to the initial state
+   (*no_implicit_conditions*)
+   rule doClearRule (doClear.wget() matches tagged Valid.d);
+      f.clear();
+   endrule
+
    //only allow the LAST enq each cycle to work, drop the others
-   method Action enq(dtyp a) if (f.notFull() && !clearCalled);
+   method Action enq(dtyp a) if (f.notFull());
       enq_data.wset(a);
    endmethod
 
-   method Action deq() if (!clearCalled);
+   method Action deq();
       f.deq();
    endmethod
 
@@ -93,7 +94,7 @@ module mkNBFIFOF(FIFOF#(dtyp)) provisos (Bits#(dtyp, szdtyp));
    endmethod
 
    method Action clear();
-      clearCalled <= True;
+      doClear.wset(True);
    endmethod
 
 endmodule

bscRuntime/memories/Speculation.bsv

@@ -1,3 +1,4 @@
+// Speculation.bsv
 package Speculation;
 
 import Vector :: *;
@@ -41,30 +42,43 @@ module mkSpecTable(SpecTable#(SpecId#(entries), bypassCnt));
       $display("Head: %d", head);
       for (Integer i = 0; i < valueOf(entries); i = i + 1)
 	 begin
-	    $display("Idx %d, InUse: %b", i, inUse[fromInteger(i)]);   
-	    $display("Idx %d, Status: %b", i, specStatus[fromInteger(i)]);
+	    $display("Idx %d, InUse: %b", i, inUse[fromInteger(i)]);
+	    $display("Idx %d, Status: %b", i, specStatus[fromInteger(i)][0]);
 	 end
    endrule
-    */
-
+   */
+   //Make sure no enq could happen during clear (takes 2 cycles)
+
    RWire#(Bool) doAlloc <- mkRWireSBR();
+   RWire#(Bool) doClear <- mkRWireSBR();
+
+   /*
+   Reg#(Bool) enabled <- mkReg(True);
+   */
+   (*conflict_free = "doAllocRule, doClearRule"*)
    (*fire_when_enabled*)
    rule doAllocRule (doAlloc.wget() matches tagged Valid.d);
-      head <= head + 1;
-      inUse[head] <= True;
-      specStatus[head][valueOf(bypassCnt)-1] <= tagged Invalid;
+        head <= head + 1;
+        inUse[head] <= True;
+        specStatus[head][valueOf(bypassCnt)-1] <= tagged Invalid;
    endrule
-   
+
    //reset to the initial state
+   (*no_implicit_conditions*)
+   rule doClearRule (doClear.wget() matches tagged Valid.d);
+        //$display("SpecTable Cleared");
+        head <= 0;
+        for (Integer i = 0; i < valueOf(entries); i = i + 1) begin
+           SpecId#(entries) lv = fromInteger(i);
+           specStatus[lv][0] <= tagged Invalid;
+           inUse[lv] <= False;
+        end
+   endrule
+
    method Action clear();
-      head <= 0;
-      for (Integer i = 0; i < valueOf(entries); i = i + 1) begin
-	 SpecId#(entries) lv = fromInteger(i);
-	 specStatus[lv][0] <= tagged Invalid;
-	 inUse[lv] <= False;
-      end
+        doClear.wset(True);
    endmethod
-   
+
     //allocate a new entry in the table to track speculation. do this in a nonblocking way
     //and just assume that only 1 client calls per cycle
    method ActionValue#(SpecId#(entries)) alloc() if (!full);

bscRuntime/memories/StgFIFOs.bsv

@@ -0,0 +1,58 @@
+// StgFIFOs.bsv
+package StgFIFOs;
+
+import Ehr :: *;
+import ConfigReg :: *;
+import FIFOF :: *;
+
+export mkStgFIFOF;
+
+// Change to a CReg, two element Queue for per cycle.
+module mkStgFIFOF(FIFOF#(dtyp)) provisos (Bits#(dtyp, szdtyp));
+
+   FIFOF#(dtyp) f <- mkFIFOF();
+   //allow multiple writes in the same cycle
+   RWire#(dtyp) enq_data <- mkRWireSBR();
+   RWire#(Bool) doClear <- mkRWireSBR();
+
+   //Make sure no enq could happen during clear (takes 2 cycles)
+
+   (*conflict_free = "doEnqRule, doFIFOClearRule"*)
+   (*fire_when_enabled, no_implicit_conditions*)
+   rule doEnqRule (enq_data.wget() matches tagged Valid.d);
+      f.enq(d);
+   endrule
+
+   (*fire_when_enabled, no_implicit_conditions*)
+   rule doFIFOClearRule (doClear.wget() matches tagged Valid.d);
+      f.clear();
+   endrule
+
+   //only allow the LAST enq each cycle to work, drop the others
+   method Action enq(dtyp a) if (f.notFull());
+      enq_data.wset(a);
+   endmethod
+
+   method Action deq();
+      f.deq();
+   endmethod
+
+   method dtyp first();
+      return f.first();
+   endmethod
+
+   method Bool notFull();
+      return f.notFull();
+   endmethod
+
+   method Bool notEmpty();
+      return f.notEmpty();
+   endmethod
+
+   method Action clear();
+      doClear.wset(True);
+   endmethod
+
+endmodule
+
+endpackage

bscRuntime/memories/tb.bsv

@@ -1,3 +1,4 @@
+// tb.bsv
 import Locks :: *;
 import Memories::*;
 import FIFO::*;

bscRuntime/verilog/BHT.v

@@ -1,3 +1,4 @@
+// BHT.v
 `ifdef BSV_ASSIGNMENT_DELAY
 `else
 `define BSV_ASSIGNMENT_DELAY

bscRuntime/verilog/BypassRF.v

@@ -1,3 +1,4 @@
+// BypassRF.v
 `ifdef BSV_ASSIGNMENT_DELAY
 `else
 `define BSV_ASSIGNMENT_DELAY

bscRuntime/verilog/CheckpointBypassRF.v

@@ -1,3 +1,4 @@
+// CheckpointBypassRF.v
 `ifdef BSV_ASSIGNMENT_DELAY
 `else
 `define BSV_ASSIGNMENT_DELAY