First actually "complete" commit

Write back stage added, proper connections made back to ID stage.  Some little tweaks are probably needed (forwarding & stalling are still not implemented), BUT load word and add work.  This most likely indicates all non-hazardous (no control, data, or structure hazards) MIPS assembly should be able to be run on this processor.

DataMem.v

@@ -13,21 +13,21 @@ module DataMem(
 	output [31:0] dataOut
 	);
 
-reg [7:0] mem [255:0];
+reg [31:0] mem [255:0];
 
 assign dataOut = mem[readAddr];
 
 initial begin
 	mem[0] = 'hA00000AA;
-	mem[1] = 'h10000011;
-	mem[2] = 'h20000022;
-	mem[3] = 'h30000033;
-	mem[4] = 'h40000044;
-	mem[5] = 'h50000055;
-	mem[6] = 'h60000066;
-	mem[7] = 'h70000077;
-	mem[8] = 'h80000088;
-	mem[9] = 'h90000099;
+	mem[4] = 'h10000011;
+	mem[8] = 'h20000022;
+	mem[12] = 'h30000033;
+	mem[16] = 'h40000044;
+	mem[20] = 'h50000055;
+	mem[24] = 'h60000066;
+	mem[28] = 'h70000077;
+	mem[32] = 'h80000088;
+	mem[36] = 'h90000099;
 end
 
 always @ (*)
@@ -36,4 +36,6 @@ always @ (*)
 			begin
 			mem[writeAddr] = dataIn;
 			end
-	end
+	end
+
+endmodule

EXE.v

@@ -1,3 +1,4 @@
+`timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
 //										
 // EXE secondary-level module								
@@ -13,7 +14,7 @@ module EXE(
 	output [4:0] RdRtout,
 	output [31:0] qbout, aluout
 	);
-wire aluSelect;
+wire [31:0] aluSelect;
 
 assign wregout = ewreg;
 assign m2regout = em2reg;
@@ -22,4 +23,6 @@ assign RdRtout = RdRtin;
 assign qbout = qb;
 
 FullMux FullMux(qb, extended, ealuimm, aluSelect);
-ALU ALU(qa, aluSelect, ealuc, aluout);
+ALU ALU(qa, aluSelect, ealuc, aluout);
+
+endmodule

EXEMEMRegister.v

@@ -7,7 +7,7 @@
 module EXEMEMRegister(
 	input clk, wregin, m2regin, wmemin,
 	input [4:0] RdRtin,
-	input [31:0] aluresultin, qbin,
+	input [31:0] qbin, aluresultin,
 	output reg wregout, m2regout, wmemout,
 	output reg [4:0] RdRtout,
 	output reg [31:0] aluresultout, qbout
@@ -20,4 +20,6 @@ always @ (posedge clk) begin
 	RdRtout = RdRtin;
 	aluresultout = aluresultin;
 	qbout = qbin;
-end
+end
+
+endmodule

FullMux.v

@@ -6,10 +6,10 @@
 
 module FullMux(
 	input [31:0] a, b,
-	input select;
-	output reg out
+	input select,
+	output [31:0] out
 	);
 
-	assign out = (select == 0?) a : b;
+	assign out = (select == 0) ?  a : b;
 
 endmodule

InstrMem.v

@@ -18,6 +18,9 @@ module InstrMem(
     initial begin
     	memory[100] = 32'b10001100001000100000000000000000;
     	memory[104] = 32'b10001100001000110000000000000100;
+    	memory[108] = 32'b10001100001001000000000000001000;
+    	memory[112] = 32'b10001100001001010000000000001100;
+    	memory[116] = 32'b00000000010010100011000000100000;
     end
 
     assign dataOut = memory[readAddr];

MEMWBRegister.v

@@ -16,7 +16,9 @@ module MEMWBRegister(
 always @ (posedge clk) begin
 	wregout = wregin;
 	m2regout = m2regin;
-	RdRtin = RdRtout;
+	RdRtout = RdRtin;
 	aluresultout = aluresultin;
 	memdataout = memdatain;
-end
+end
+
+endmodule

RegFile.v

@@ -11,13 +11,21 @@
 module RegFile(
 	input clk, enableWrite,
     input [4:0] addrA, addrB, writeAddr,
-    input [31:0] writeData, dataOutA, dataOutB
+    input [31:0] writeData, 
+    output [31:0] dataOutA, dataOutB
     );
 
 reg [31:0] regs [31:0];
 
 initial begin
-	regs[1] = 32'b00000000000000000000000000000000;
+	regs[0] = 32'd0;
+	regs[1] = 32'd0;
+	regs[2] = 32'd0;
+	regs[3] = 32'd0;
+	regs[4] = 32'd0;
+	regs[5] = 32'd0;
+	regs[6] = 32'd0;
+	regs[10] = 32'd0;
 end
 
 assign dataOutA = regs[addrA];

WB.v

@@ -0,0 +1,24 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+//																				//
+// CMPEN 331 Spring 2017														//
+// Code by John Huddleston (Section 2)											//
+// WB secondary-level module													//
+// 																				//
+//////////////////////////////////////////////////////////////////////////////////
+
+module WB(
+	input wregin, m2reg,
+	input [4:0] RdRtin,
+	input [31:0] aluresult, memdata,
+	output wregout,
+	output [4:0] RdRtout,
+	output [31:0] writedata
+	);
+
+assign wregout = wregin;
+assign RdRtout = RdRtin;
+
+FullMux FullMux(aluresult, memdata, m2reg, writedata);
+
+endmodule

alu.v

@@ -11,7 +11,7 @@
 module ALU(
 	input [31:0] a, b,
 	input [3:0] contr,
-	output [31:0] out
+	output reg [31:0] out
 	);
 
 always @ (*) begin
@@ -47,6 +47,8 @@ always @ (*) begin
 	4'b1100: begin
 		out = ~(a | b);
 	end
+
+	endcase
 
 end
 

cpu.v

@@ -3,44 +3,28 @@
 //                                                                              //
 // CMPEN 331 Spring 2017                                                        //
 // Code by John Huddleston (Section 2)                                          //
-// Top level module		                                                        //
+// New CPU top-level module                                                     //
 //                                                                              //
 //////////////////////////////////////////////////////////////////////////////////
 
-
 module cpu(
-    input clk
-    );
-
-	// Wires for Lab 4 components
-	wire [31:0] instrAddr, newInstrAddr, instr2reg, instr, tempWData, regOutA, regOutB, extended;
-	wire tempWReg, wreg, m2reg, wmem, aluimm;
-	wire[3:0] aluc;
-	wire [4:0] RdRt, tempWAddr;
-
-	// Wires for EXE and EXE/MEM register components
-	wire wreg2exe, m2reg2exe, wmem2exe, aluimm2exe, wreg2exemem, m2reg2exemem, wmem2exemem;
-	wire [3:0] aluc2exe;
-	wire [4:0] RdRt2exe, RdRt2exemem;
-	wire [31:0] regOutA2exe, regOutB2exe, extended2exe, aluresult2exemem, qb2exemem;
+	input clk
+	);
 
-	// Wires for MEM and MEM/WB components
-	wire wreg2mem, m2reg2mem, wmem2mem, wreg2memwb, m2reg2memwb;
-	wire [4:0] RdRt2mem, RdRt2memwb;
-	wire [31:0] aluresult2mem, qb2mem, aluresult2memwb, dataout2memwb;
+wire e0, f0, g0, i0, n0, o0, p0, r0, w0, x0, y0, c1, d1, e1, i1, j1, n1, o1, s1;
+wire [3:0] h0, q0;
+wire [4:0] j0, s0, z0, f1, k1, p1, t1;
+wire [31:0] a0, b0, c0, d0, k0, l0, m0, t0, u0, v0, a1, b1, g1, h1, l1, m1, q1, r1, u1;
 
-	PCRegister PCRegister(clk, newInstrAddr, instrAddr);
-	IF IF(instrAddr, newInstrAddr, instr2reg);
-	IFIDRegister IFIDRegister(instr2reg, instr, clk);
-	ID ID(instr, tempWData, clk, tempWReg, tempWAddr, wreg, m2reg, wmem, aluc, aluimm, RdRt, regOutA, regOutB, extended);
-	IDEXERegister IDEXERegister(wreg, m2reg, wmem, aluimm, clk, aluc, RdRt, regOutA, regOutB, extended, wreg2exe, 
-		m2reg2exe, wmem2exe, aluimm2exe, aluc2exe, RdRt2exe, regOutA2exe, regOutB2exe, extended2exe);
-	EXE EXE(wreg2exe, m2reg2exe, wmem2exe, aluimm2exe, aluc2exe, RdRt2exe, regOutA2exe, regOutB2exe, extended2exe, 
-		wreg2exemem, m2reg2exemem, wmem2exemem, RdRt2exemem, qb2exemem, aluresult2exemem);
-	EXEMEMRegister EXEMEMRegister(clk, wreg2exemem, m2reg2exemem, wmem2exemem, RdRt2exemem, aluresult2exemem, qb2exemem,
-		wreg2mem, m2reg2mem, wmem2mem, RdRt2mem, aluresult2mem, dataout2mem);
-	MEM MEM(wreg2mem, m2reg2mem, wmem2mem, RdRt2mem, aluresult2mem, qb2mem, wreg2memwb, m2reg2memwb, RdRt2memwb, 
-		aluresult2memwb, dataout2memwb);
-	MEMWBRegister MEMWBRegister(clk, wreg2memwb, m2reg2memwb, RdRt2memwb, aluresult2memwb, dataout2memwb);
+PCRegister PCRegister(clk, b0, a0);
+IF IF(a0, b0, c0);
+IFIDRegister IFIDRegister(c0, d0, clk);
+ID ID(d0, u1, clk, s1, t1, e0, f0, g0, h0, i0, j0, k0, l0, m0);
+IDEXERegister IDEXERegister(e0, f0, g0, i0, clk, h0, j0, k0, l0, m0, n0, o0, p0, r0, q0, s0, t0, u0, v0);
+EXE EXE(n0, o0, p0, r0, q0, s0, t0, u0, v0, w0, x0, y0, z0, a1, b1);
+EXEMEMRegister EXEMEMRegister(clk, w0, x0, y0, z0, a1, b1, c1, d1, e1, f1, g1, h1);
+MEM MEM(c1, d1, e1, f1, g1, h1, i1, j1, k1, l1, m1);
+MEMWBRegister MEMWBRegister(clk, i1, j1, k1, l1, m1, n1, o1, p1, q1, r1);
+WB WB(n1, o1, p1, q1, r1, s1, t1, u1);
 
-endmodule
+endmodule