Update README.md

README.md

@@ -11,6 +11,4 @@ This is a simple Verilog implementation of a MIPS processor datapath utilizing a
                             iv.  Memory Access
                             v.   Write-back
                             
-Currently the first two stages are operational up to what can be tested at the EXE/MEM register.  
-The plan is to finish up the last 3 stages (current work being done on stages iii and iv) and add
-a forwarding unit.
+Currently there is one bug in the MEM/WB register, and there is no WB stage.  Everything else is operational.  Branching not implemented, doesn't seem like it will be (for the class, I'll get to it later), and forwarding will most likely be implemented after the WB stage.