Skip to content

Commit

Permalink
Multiple updates, just reuploaded all files
Browse files Browse the repository at this point in the history
  • Loading branch information
@JohnHuddleston
JohnHuddleston authored Apr 18, 2017
1 parent 57e0f17 commit 95542f3
Show file tree
Hide file tree
Showing 15 changed files with 76 additions and 24 deletions.
16 changes: 10 additions & 6 deletions ControlUnit.v
View file
Original file line number Diff line number Diff line change
@@ -1,12 +1,16 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// //
// Control unit module //
// //
// //
// CMPEN 331 Spring 2017 //
// Code by John Huddleston (Section 2) //
// Control unit module //
// //
//////////////////////////////////////////////////////////////////////////////////
// //
// NOTE: Not all instructions are implemented yet. //
// //
// //
// NOTE: Not all instructions are implemented yet. Lab 4 requires only LW to //
// be defined, but I have defined control outputs for a few other //
// (simple) instructions to be prepared. //
// //
//////////////////////////////////////////////////////////////////////////////////


Expand Down
10 changes: 6 additions & 4 deletions DataMem.v
View file
Original file line number Diff line number Diff line change
@@ -1,8 +1,10 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// //
// Data memory module //
// //
// //
// CMPEN 331 Spring 2017 //
// Code by John Huddleston (Section 2) //
// Data memory module //
// //
//////////////////////////////////////////////////////////////////////////////////

module DataMem(
Expand Down Expand Up @@ -34,4 +36,4 @@ always @ (*)
begin
mem[writeAddr] = dataIn;
end
end
end
8 changes: 5 additions & 3 deletions ID.v
View file
Original file line number Diff line number Diff line change
@@ -1,8 +1,10 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// //
// ID secondary-level module //
// //
// //
// CMPEN 331 Spring 2017 //
// Code by John Huddleston (Section 2) //
// ID secondary level module //
// //
//////////////////////////////////////////////////////////////////////////////////


Expand Down
8 changes: 5 additions & 3 deletions IDEXERegister.v
View file
Original file line number Diff line number Diff line change
@@ -1,8 +1,10 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// ID/EXE register module
//
// //
// CMPEN 331 Spring 2017 //
// Code by John Huddleston (Section 2) //
// ID/EXE register module //
// //
//////////////////////////////////////////////////////////////////////////////////


Expand Down
2 changes: 2 additions & 0 deletions IF.v
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// //
// CMPEN 331 Spring 2017 //
// Code by John Huddleston (Section 2) //
// IF secondary level module //
// //
//////////////////////////////////////////////////////////////////////////////////
Expand Down
2 changes: 2 additions & 0 deletions IFIDRegister.v
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// //
// CMPEN 331 Spring 2017 //
// Code by John Huddleston (Section 2) //
// IF/ID register module //
// //
//////////////////////////////////////////////////////////////////////////////////
Expand Down
2 changes: 2 additions & 0 deletions InstrMem.v
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// //
// CMPEN 331 Spring 2017 //
// Code by John Huddleston (Section 2) //
// Instruction memory module //
// //
//////////////////////////////////////////////////////////////////////////////////
Expand Down
2 changes: 2 additions & 0 deletions MEM.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,12 +9,14 @@ module MEM(
input [4:0] RdRtin,
input [31:0] aluresult, qb,
output wregout, m2regout,
output [4:0] RdRtout,
output [31:0] aluresultout, dataout
);

assign wregout = wregin;
assign m2regout = m2regin;
assign aluresultout = aluresult;
assign RdRtout = RdRtin;

DataMem DataMem(aluresult, aluresult, qb, wmemin, dataout);

Expand Down
2 changes: 2 additions & 0 deletions PCRegister.v
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// //
// CMPEN 331 Spring 2017 //
// Code by John Huddleston (Section 2) //
// Program counter module //
// //
//////////////////////////////////////////////////////////////////////////////////
Expand Down
2 changes: 2 additions & 0 deletions RegFile.v
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// //
// CMPEN 331 Spring 2017 //
// Code by John Huddleston (Section 2) //
// Register file module //
// //
//////////////////////////////////////////////////////////////////////////////////
Expand Down
2 changes: 2 additions & 0 deletions RegMux.v
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// //
// CMPEN 331 Spring 2017 //
// Code by John Huddleston (Section 2) //
// Generic multiplexer module //
// //
//////////////////////////////////////////////////////////////////////////////////
Expand Down
2 changes: 2 additions & 0 deletions SignExtender.v
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// //
// CMPEN 331 Spring 2017 //
// Code by John Huddleston (Section 2) //
// Sign extender module //
// //
//////////////////////////////////////////////////////////////////////////////////
Expand Down
2 changes: 2 additions & 0 deletions adder.v
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// //
// CMPEN 331 Spring 2017 //
// Code by John Huddleston (Section 2) //
// Generic 32 bit adder //
// //
//////////////////////////////////////////////////////////////////////////////////
Expand Down
14 changes: 8 additions & 6 deletions alu.v
View file
Original file line number Diff line number Diff line change
@@ -1,9 +1,11 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// //
// Arithmetic logic unit //
// Overflow and zero outputs not yet implemented //
// //
// //
// CMPEN 331 Spring 2017 //
// Code by John Huddleston (Section 2) //
// Arithmetic logic unit //
// Overflow and zero outputs not yet implemented //
// //
//////////////////////////////////////////////////////////////////////////////////

module ALU(
Expand Down Expand Up @@ -47,5 +49,5 @@ always @ (*) begin
end

end
endmodule

endmodule
26 changes: 24 additions & 2 deletions cpu.v
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,9 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// //
// Top level module //
// CMPEN 331 Spring 2017 //
// Code by John Huddleston (Section 2) //
// Top level module //
// //
//////////////////////////////////////////////////////////////////////////////////

Expand All @@ -10,15 +12,35 @@ module cpu(
input clk
);

// Wires for Lab 4 components
wire [31:0] instrAddr, newInstrAddr, instr2reg, instr, tempWData, regOutA, regOutB, extended;
wire tempWReg, wreg, m2reg, wmem, aluimm;
wire[3:0] aluc;
wire [4:0] RdRt, tempWAddr;

// Wires for EXE and EXE/MEM register components
wire wreg2exe, m2reg2exe, wmem2exe, aluimm2exe, wreg2exemem, m2reg2exemem, wmem2exemem;
wire [3:0] aluc2exe;
wire [4:0] RdRt2exe, RdRt2exemem;
wire [31:0] regOutA2exe, regOutB2exe, extended2exe, aluresult2exemem, qb2exemem;

// Wires for MEM and MEM/WB components
wire wreg2mem, m2reg2mem, wmem2mem, wreg2memwb, m2reg2memwb;
wire [4:0] RdRt2mem, RdRt2memwb;
wire [31:0] aluresult2mem, qb2mem, aluresult2memwb, dataout2memwb;

PCRegister PCRegister(clk, newInstrAddr, instrAddr);
IF IF(instrAddr, newInstrAddr, instr2reg);
IFIDRegister IFIDRegister(instr2reg, instr, clk);
ID ID(instr, tempWData, clk, tempWReg, tempWAddr, wreg, m2reg, wmem, aluc, aluimm, RdRt, regOutA, regOutB, extended);
IDEXERegister IDEXERegister(wreg, m2reg, wmem, aluimm, clk, aluc, RdRt, regOutA, regOutB, extended);
IDEXERegister IDEXERegister(wreg, m2reg, wmem, aluimm, clk, aluc, RdRt, regOutA, regOutB, extended, wreg2exe,
m2reg2exe, wmem2exe, aluimm2exe, aluc2exe, RdRt2exe, regOutA2exe, regOutB2exe, extended2exe);
EXE EXE(wreg2exe, m2reg2exe, wmem2exe, aluimm2exe, aluc2exe, RdRt2exe, regOutA2exe, regOutB2exe, extended2exe,
wreg2exemem, m2reg2exemem, wmem2exemem, RdRt2exemem, qb2exemem, aluresult2exemem);
EXEMEMRegister EXEMEMRegister(clk, wreg2exemem, m2reg2exemem, wmem2exemem, RdRt2exemem, aluresult2exemem, qb2exemem,
wreg2mem, m2reg2mem, wmem2mem, RdRt2mem, aluresult2mem, dataout2mem);
MEM MEM(wreg2mem, m2reg2mem, wmem2mem, RdRt2mem, aluresult2mem, qb2mem, wreg2memwb, m2reg2memwb, RdRt2memwb,
aluresult2memwb, dataout2memwb);
MEMWBRegister MEMWBRegister(clk, wreg2memwb, m2reg2memwb, RdRt2memwb, aluresult2memwb, dataout2memwb);

endmodule

0 comments on commit 95542f3

Please sign in to comment.