drivers: spi: siwx91x: SPI driver fixes to enable higher burst rates #99860

smalae · 2025-11-23T13:11:37Z

Setting INTF PLL to 160 MHz so GSPI has a stable, high-rate base clock, and QSPI gets the expected 80 MHz.
Rounding the GSPI frequency down to a valid step derived from the INTF PLL (f = PLL/(2*div)), and logging the requested vs programmed rate.
Enabling higher GPDMA burst sizes (1/2/4) when safe (SPI ≥ 10 MHz and both channels use GPDMA). The burst size is selected from the largest value that satisfies TX/RX buffer alignment, and FIFO thresholds are set accordingly. A temporary limitation notes DMA flow-control issues at low SPI rates, so bursts are gated behind the 10 MHz threshold.
Align mosi_overrun to 32 bytes
Fixing 16-bit transfers by swapping write/read data paths in the GSPI controller (GSPI_CONFIG2_b), ensuring the correct signal presentation on the SPI lines.
Guarding async callback registration to avoid build errors when using blocking DMA transfers without CONFIG_SPI_ASYNC.
Updating tests: increase CONFIG_SPI_IDEAL_TRANSFER_DURATION_SCALING from 24 → 26 to account for the (slightly) increased transfer time due to burst-size calculation.
Enable the spi_loopback test for the PSRAM board siwx917_rb4342a.

The GSPI and QSPI peripherals run on the interface PLL clock. To ensure correct operation, the interface PLL frequency should be set to 160 MHz. This provides a base clock of 80 MHz to the QSPI peripheral, which matches its required operating frequency. The GSPI peripheral can continue to operate at higher frequencies as it receives the full interface PLL clock. Signed-off-by: Sai Santhosh Malae <[email protected]>

tbursztyka · 2025-11-26T20:41:49Z

drivers/spi/spi_silabs_siwx91x_gspi.c

 	clock_control_subsys_t clock_subsys;
 	const struct pinctrl_dev_config *pcfg;
-	uint8_t mosi_overrun __aligned(4);
+	uint8_t mosi_overrun __aligned(32);


Why this change?

This update ensures proper buffer alignment when using the SI91x GPDMA driver. A separate commit has been created to address this issue explicitly.

jerome-pouiller · 2025-11-27T10:56:30Z

drivers/spi/spi_silabs_siwx91x_gspi.c

+				  uint32_t *div_out)
+{
+	/* Calculate divider that ensures freq <= requested */
+	uint32_t divider = (clock_hz + (2U * requested_hz) - 1U) / (2U * requested_hz);


uint32_t divider = DIV_ROUND_UP(clock_hz, 2 * requested_hz);

jerome-pouiller · 2025-11-27T10:57:12Z

drivers/spi/spi_silabs_siwx91x_gspi.c

+	/* Compute the actual achievable frequency */
+	uint32_t actual_hz = clock_hz / (2U * divider);
+
+	if (divider == 0U) {


If divider == 0, actual_hz = clock_hz / (2U * divider) has already raised a fault.

jerome-pouiller · 2025-11-27T11:14:39Z

drivers/spi/spi_silabs_siwx91x_gspi.c

+	}
+
+	return 1;
+}


I believe this function is more complex than required. I believe we can get the same result with:

static int gspi_siwx91x_burst_size_buf(const struct spi_buf *spi_buf) { int burst_len = 4; if (!ctx->current_tx[i].len || !ctx->current_tx[i].buf) { return burst_len; } burst_len = MIN(burst_len, BIT(find_lsb_set(spi_buf->buf) - 1)); burst_len = MIN(burst_len, BIT(find_lsb_set(spi_buf->len) - 1)); return burst_len; } static int gspi_siwx91x_burst_size(struct spi_context *ctx) { int burst_len = 4; for (int i = 0; i < ctx->tx_count; i++) { burst_len = MIN(burst_len, gspi_siwx91x_burst_size_buf(ctx->current_tx + i)); } for (int i = 0; i < ctx->rx_count; i++) { burst_len = MIN(burst_len, gspi_siwx91x_burst_size_buf(ctx->current_rx + i)); } return burst_len; }

Updated as per the suggestion with minor adjustments.

jerome-pouiller · 2025-11-27T11:22:05Z

tests/drivers/spi/spi_loopback/testcase.yaml

+      - CONFIG_SPI_SILABS_SIWX91X_GSPI_DMA=y
+      - CONFIG_SPI_IDEAL_TRANSFER_DURATION_SCALING=26
+    extra_args:
+      - DTC_OVERLAY_FILE="boards/siwx917_rb4338a.overlay"


I suggest to introduce boards/siwx917_rb4342a.overlay rather than using extra_args:

jerome-pouiller · 2025-11-27T11:23:32Z

tests/drivers/spi/spi_loopback/testcase.yaml

+      - siwx917_rb4342a
+    extra_configs:
+      - CONFIG_SPI_SILABS_SIWX91X_GSPI_DMA=y
+      - CONFIG_SPI_IDEAL_TRANSFER_DURATION_SCALING=26


Redundant with the .conf file, no?

Add gspi_siwx91x_pick_lower_freq() to select the nearest lower supported GSPI clock frequency based on the requested value. The GSPI clock can operate only at discrete frequencies such as 80 MHz, 40 MHz, 26.6 MHz, 20 MHz, and so on (80 MHz divided by integer factors). If the requested frequency does not match one of these valid steps, it is rounded down to the nearest lower supported frequency. The driver now logs both the requested and the actual programmed frequency along with the divider value, helping users verify the effective SPI clock configuration. Signed-off-by: Sai Santhosh Malae <[email protected]>

Enable higher SPI burst sizes when using GPDMA to improve throughput. Bursts are only enabled when both TX and RX channels use GPDMA and the SPI clock frequency is at least 10 MHz, as DMA flow control is unreliable at lower SPI rates. Signed-off-by: Sai Santhosh Malae <[email protected]>

Updated mosi_overrun alignment from 4 bytes to 32 bytes to ensure compatibility with the GPDMA driver. This prevents alignment-related errors during DMA transfers. Signed-off-by: Sai Santhosh Malae <[email protected]>

Swap the write and read data paths within the GSPI controller to ensure correct data is seen on the SPI lines during 16-bit transfers. Signed-off-by: Sai Santhosh Malae <[email protected]>

Guard callback registration with CONFIG_SPI_ASYNC to avoid build error for blocking SPI transfers using DMA Signed-off-by: Sai Santhosh Malae <[email protected]>

Increase CONFIG_SPI_IDEAL_TRANSFER_DURATION_SCALING to compensate for the additional burst size calculation in the SPI driver, which slightly increases transfer time. Signed-off-by: Sai Santhosh Malae <[email protected]>

Add overlay and config files for siwx917_rb4342a to enable the spi_loopback test. Signed-off-by: Sai Santhosh Malae <[email protected]>

sonarqubecloud · 2025-11-29T14:55:57Z

Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

smalae changed the title ~~Spi gpdma variable burst sizes~~ drivers: spi: siwx91x: SPI driver fixes to enable higher burst rates Nov 23, 2025

smalae force-pushed the spi-gpdma-variable-burst-sizes branch from 3b4530b to 3453c6f Compare November 23, 2025 13:20

smalae requested a review from jerome-pouiller November 23, 2025 13:24

smalae force-pushed the spi-gpdma-variable-burst-sizes branch from 3453c6f to 45a9da9 Compare November 24, 2025 05:00

smalae marked this pull request as ready for review November 25, 2025 14:15

zephyrbot added area: Boards/SoCs area: Clock Control platform: Silabs Silicon Labs area: SPI SPI bus area: Tests Issues related to a particular existing or missing test labels Nov 25, 2025

zephyrbot requested review from Martinhoff-maker, asmellby, decsny, jhedberg, nashif, nordic-krch, tbursztyka and teburd November 25, 2025 14:17

zephyrbot assigned tbursztyka Nov 25, 2025

tbursztyka reviewed Nov 26, 2025

View reviewed changes

jerome-pouiller reviewed Nov 27, 2025

View reviewed changes

smalae force-pushed the spi-gpdma-variable-burst-sizes branch from 45a9da9 to 1ceb193 Compare November 29, 2025 14:13

smalae added 6 commits November 29, 2025 19:51

drivers: spi: siwx91x: Align mosi_overrun to 32 bytes

668ca2c

Updated mosi_overrun alignment from 4 bytes to 32 bytes to ensure compatibility with the GPDMA driver. This prevents alignment-related errors during DMA transfers. Signed-off-by: Sai Santhosh Malae <[email protected]>

drivers: spi: siwx91x: Swap write and read data inside GSPI controller

f3da34a

Swap the write and read data paths within the GSPI controller to ensure correct data is seen on the SPI lines during 16-bit transfers. Signed-off-by: Sai Santhosh Malae <[email protected]>

drivers: spi: siwx91x: Guard callback registration

b94e949

Guard callback registration with CONFIG_SPI_ASYNC to avoid build error for blocking SPI transfers using DMA Signed-off-by: Sai Santhosh Malae <[email protected]>

tests: drivers: spi: siwx91x: Adjust transfer scaling factor

bf8b761

Increase CONFIG_SPI_IDEAL_TRANSFER_DURATION_SCALING to compensate for the additional burst size calculation in the SPI driver, which slightly increases transfer time. Signed-off-by: Sai Santhosh Malae <[email protected]>

tests: drivers: spi: siwx91x: Enable spi_loopback test for PSRAM board

05fa966

Add overlay and config files for siwx917_rb4342a to enable the spi_loopback test. Signed-off-by: Sai Santhosh Malae <[email protected]>

smalae force-pushed the spi-gpdma-variable-burst-sizes branch from 1ceb193 to 05fa966 Compare November 29, 2025 14:28

smalae requested review from jerome-pouiller and tbursztyka November 29, 2025 14:34

drivers: spi: siwx91x: SPI driver fixes to enable higher burst rates #99860

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drivers: spi: siwx91x: SPI driver fixes to enable higher burst rates #99860

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smalae commented Nov 23, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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jerome-pouiller Nov 27, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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sonarqubecloud bot commented Nov 29, 2025

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smalae commented Nov 23, 2025 •

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