Drivers: DMA: Infineon PSE84 Cat1 PDL driver #98035
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Adding binding file for IFX Cat1 DMA PDL based driver implementation. Signed-off-by: John Batch <[email protected]>
Updates DMA includes from the modules needed for DMA PDL based driver implementation. Signed-off-by: John Batch <[email protected]>
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Adds Infineon Cat1 PDL based driver for DMA. Signed-off-by: John Batch <[email protected]>
Adds overlays to enable test runs for DMA on the following tests: -tests/drivers/dma/chan_blen_transfer -tests/drivers/dma/loop_transfer Signed-off-by: John Batch <[email protected]>
Adds support to the kit_pse84_eval board for DMA. Signed-off-by: John Batch <[email protected]>
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Given that PDL refers to Peripheral Driver Library, a software component, the hw device binding should have nothing to do with it.
Also, there already is a binding for this device, dts/bindings/dma/infineon,cat1-dma.yaml.
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This looks like a duplicate of the existing dma_ifx_cat1.c driver to me. With maybe some added features. There shouldn't be two of these unless they are in fact two distinct IP blocks with different register maps and/or HAL interfaces.
The binding has a large number of options that don't appear to be used. These really should be added as they are required. By exposing these properties you are giving the appearance to someone creating a board port that these are configurable when they are not. That'll likely lead to some confusion.
| data->channels[channel].error_callback_dis = config->error_callback_dis; | ||
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| /* Lock and page in the channel configuration */ | ||
| uint32_t key = irq_lock(); |
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While this is ok, its not great to block interrupts while translating the descriptors. I get the reasoning here is in part because you have a single pool of descriptors of each dma that is shared among all channels. sys_mem_blocks could be used instead at a small cost to maintain the shared pool per dma instance.
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| /* initialize descriptor */ | ||
| dma_status = Cy_DMA_Descriptor_Init(descriptor, &descriptor_config); |
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It's unclear from the HAL usage here, but if registers are setup per channel then no locking at all should be needed. If some register is shared, a spin lock around the shared register updates is all that should be needed.
| * cache and will lead to errors) | ||
| */ | ||
| #ifdef CONFIG_CPU_HAS_DCACHE | ||
| SCB_InvalidateDCache(); |
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sys_cache_data_invd_all() though this is a bit of a shotgun approach
| * written back to the memory | ||
| */ | ||
| #ifdef CONFIG_CPU_HAS_DCACHE | ||
| SCB_CleanDCache(); |
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Adding Infineon PDL based driver to support DMA on the PSOC Edge 84 microcontroller family. Adds support for the following tests: