STM32: Add STM32C092 SoC support and NUCLEO-C092RC #93263
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zephyrbot
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platform: STM32
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Jul 19, 2025
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| .. zephyr:board-supported-runners:: | ||
| Nucleo C092RE board includes an ST-LINK/V2-1 embedded debug tool interface. |
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| Nucleo C092RE board includes an ST-LINK/V2-1 embedded debug tool interface. | |
| Nucleo C092RC board includes an ST-LINK/V2-1 embedded debug tool interface. |
Please check for similar typos you might have elsewhere
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Thanks for spotting the typo. Should be fixed now.
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There is a typo in message for commit tests: drivers: uart: uart_async_api: add nucleo_c092rc overlay (STM32CO instead of STM32C0).
The following commits should come after the board is introduced:
tests: drivers: adc: adc_api: add overlay for nucleo_c092rctests: drivers: uart: uart_async_api: add nucleo_c092rc overlaytests: drivers: counter: counter_basic_api: add nucleo_c092rc overlay
+ some remarks but otherwise LGTM on surface
Adds SoC support for the STM32C091, and the STM32C092 SoCs which are part of the STM32C0 series. Signed-off-by: Thomas Stranger <[email protected]>
On STM32C092 variants CAN-FD is supported, and the clock source can be chosen in the CCIPR1 register. This commit adds the helper to prepare that choice for the register. Signed-off-by: Thomas Stranger <[email protected]>
Add dts support for the STM32C091 and STM32C092 SoCs, that are part of the STM32C0 series. Signed-off-by: Thomas Stranger <[email protected]>
Add the counter nodes (compat st,stm32-counter) to all timers of the STM32C0 series. Signed-off-by: Thomas Stranger <[email protected]>
Adds definitions for the nucleo_c092rc supporting the STM32C092RC entry-level MCU with CAN-FD support. The series does not have a pll, so with the given 48MHz CAN core clock frequency the internal timing calculation can't find parameters for 5MHz data bitrate, and for 8MHz they have an error of 84/1000. Signed-off-by: Thomas Stranger <[email protected]>
Add an overlay to use adc1 channel 0 (on PA0) for testing. Signed-off-by: Thomas Stranger <[email protected]>
Add a overlay for the nucleo_c092 testing usart4 and dma channels 6 and 7. These are all not available in smaller STM32C0 SoCs. Signed-off-by: Thomas Stranger <[email protected]>
Add a overlay to the counter_basic_api test to enable the counter node of TIM2, TIM3, and TIM14 to TIM17. Signed-off-by: Thomas Stranger <[email protected]>
Add an overlay to the st specific power_mgmt wkup_pins sample for the nucleo_c092rc board. The user_button on pc13 is used as the wakeup-src. Signed-off-by: Thomas Stranger <[email protected]>
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| reg = <0x2>; | ||
| wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_NOT_MUXED>; |
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Suggested change
| reg = <0x2>; | |
| wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_NOT_MUXED>; | |
| reg = <0x2>; | |
| wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_NOT_MUXED>; |
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| reg = <0x5>; | ||
| wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_NOT_MUXED>; |
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Suggested change
| reg = <0x5>; | |
| wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_NOT_MUXED>; | |
| reg = <0x5>; | |
| wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_NOT_MUXED>; |
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| reg = <0x6>; | ||
| wkup-gpios = <&gpiob 5 STM32_PWR_WKUP_PIN_NOT_MUXED>; |
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Suggested change
| reg = <0x6>; | |
| wkup-gpios = <&gpiob 5 STM32_PWR_WKUP_PIN_NOT_MUXED>; | |
| reg = <0x6>; | |
| wkup-gpios = <&gpiob 5 STM32_PWR_WKUP_PIN_NOT_MUXED>; |
| reg-names = "m_can", "message_ram"; | ||
| interrupts = <30 0>, <31 0>; | ||
| interrupt-names = "int0", "int1"; | ||
| clocks = <&rcc STM32_CLOCK(APB1, 12U)>; |
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U suffix should not be used in DTS (yes, the entire file uses it...... I really ought to fix this one day)
Suggested change
| clocks = <&rcc STM32_CLOCK(APB1, 12U)>; | |
| clocks = <&rcc STM32_CLOCK(APB1, 12)>; |
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| clocks = <&rcc STM32_CLOCK(APB1_2, 16U)>; | ||
| resets = <&rctl STM32_RESET(APB1H, 16U)>; |
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Suggested change
| clocks = <&rcc STM32_CLOCK(APB1_2, 16U)>; | |
| resets = <&rctl STM32_RESET(APB1H, 16U)>; | |
| clocks = <&rcc STM32_CLOCK(APB1_2, 16)>; | |
| resets = <&rctl STM32_RESET(APB1H, 16)>; |
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| clocks = <&rcc STM32_CLOCK(APB1, 18U)>; | ||
| resets = <&rctl STM32_RESET(APB1L, 18U)>; |
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Suggested change
| clocks = <&rcc STM32_CLOCK(APB1, 18U)>; | |
| resets = <&rctl STM32_RESET(APB1L, 18U)>; | |
| clocks = <&rcc STM32_CLOCK(APB1, 18)>; | |
| resets = <&rctl STM32_RESET(APB1L, 18)>; |
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| clocks = <&rcc STM32_CLOCK(APB1, 19U)>; | ||
| resets = <&rctl STM32_RESET(APB1L, 19U)>; |
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Suggested change
| clocks = <&rcc STM32_CLOCK(APB1, 19U)>; | |
| resets = <&rctl STM32_RESET(APB1L, 19U)>; | |
| clocks = <&rcc STM32_CLOCK(APB1, 19)>; | |
| resets = <&rctl STM32_RESET(APB1L, 19)>; |
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Add STM32C091/STM32C092 as a member of the STM32C0 family with additional timer, serial interfaces and CAN-FD(C092 only) support.