boards: nxp: imx95_evk_15x15: add i.MX 95 15x15 LPDDR4x EVK variant

boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts

@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include <nxp/nxp_mimx95_a55.dtsi>
+#include <nxp/nxp_mimx95_19x19_a55.dtsi>
 #include "imx95_evk-pinctrl.dtsi"
 
 / {

boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.dts

@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include <nxp/nxp_mimx95_a55.dtsi>
+#include <nxp/nxp_mimx95_19x19_a55.dtsi>
 #include "imx95_evk-pinctrl.dtsi"
 
 / {

boards/nxp/imx95_evk_15x15/Kconfig.imx95_evk_15x15

@@ -0,0 +1,6 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_IMX95_EVK_15X15
+	select SOC_MIMX9596_A55 if BOARD_IMX95_EVK_15X15_MIMX9596_A55
+	select SOC_PART_NUMBER_MIMX9596AVTXN

boards/nxp/imx95_evk_15x15/board.yml

@@ -0,0 +1,6 @@
+board:
+  name: imx95_evk_15x15
+  full_name: i.MX95 15x15 EVK
+  vendor: nxp
+  socs:
+  - name: mimx9596

boards/nxp/imx95_evk_15x15/doc/index.rst

@@ -0,0 +1,138 @@
+.. zephyr:board:: imx95_evk_15x15
+
+Overview
+********
+
+The i.MX95 EVK (IMX95LP4XEVK-15) board is a platform designed to show the
+most commonly used features of the i.MX 95 applications processor.
+It is an entry-level development board, which helps developers to get familiar
+with the processor before investing a large amount of resources in more
+specific designs. The i.MX 95 device on the board comes in a compact
+15 x 15 mm package.
+
+Hardware
+********
+
+- i.MX 95 applications processor
+
+  - The processor integrates up to six Arm Cortex-A55 cores, and supports
+    functional safety with built-in Arm Cortex-M33 and -M7 cores
+
+- DRAM memory: 8-Gbit LPDDR4x DRAM
+- eMMC: 64 GB Micron eMMC
+- USB interface: Two USB ports: Type-A and Type-C
+- Audio codec interface
+
+  - One audio codec WM8962B
+  - One 3.5 mm 4-pole CTIA standard audio jack
+  - One 4-pin connector to connect speaker
+
+- Ethernet interface
+
+  - ENET2 controller
+
+    - Supports 100 Mbit/s or 1000 Mbit/s RGMII Ethernet with one RJ45
+      connector connected with an external PHY, RTL8211
+
+  - ENET1 controller
+
+    - Supports 100 Mbit/s or 1000 Mbit/s RGMII Ethernet with one RJ45
+      connector connected with an external PHY, RTL8211
+
+- M.2 interface: One Wi-Fi/Bluetooth Murata Type-2EL module based on NXP AW612
+  chip supporting 1x1 Wi-Fi 6 and Bluetooth 5.3
+
+- MIPI CSI interface: Connects to one 22-pin or 36-pin miniSAS connector using x4 lane
+  configuration
+- MIPI CSIDSI interface: Connects to one 36-pin miniSAS connector using x4 lane
+  configuration
+- LVDS interface: two mini-SAS connectors each with x4-lane configuration
+- CAN interface: One 4-pin CAN headers for external connection
+- SD card interface: one 4-bit SD3.0 microSD card
+- I2C interface: I2C1 to I2C6 controllers
+- FT4232H I2C interface: PCT2075 temperature sensor and current monitoring devices
+- ADC interface: two 4-channel ADC header
+- Debug interface
+
+  - One USB-to-UART/MPSSE device, FT4232H
+  - One USB 2.0 Type-C connector (J31) for FT4232H provides quad serial ports
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+System Clock
+------------
+
+This board configuration uses a system clock frequency of 24 MHz for Cortex-A55.
+Cortex-A55 Core runs up to 1.8 GHz.
+
+Serial Port
+-----------
+
+This board configuration uses a single serial communication channel with the
+CPU's UART1 for Cortex-A55.
+
+Programming and Debugging (A55)
+*******************************
+
+Use this configuration to run basic Zephyr applications and kernel tests,
+for example, with the :zephyr:code-sample:`synchronization` sample:
+
+1. Build and run the Non-SMP application
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/synchronization
+   :host-os: unix
+   :board: imx95_evk_15x15/mimx9596/a55
+   :goals: build
+
+This will build an image (zephyr.bin) with the synchronization sample app.
+
+Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and
+plug the SD card into the board. Power it up and stop the u-boot execution at
+prompt.
+
+Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1:
+
+.. code-block:: console
+
+    fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; cpu 1 release 0xd0000000
+
+
+Or use the following command to kick zephyr.bin to Cortex-A55 Core0:
+
+.. code-block:: console
+
+    fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; go 0xd0000000
+
+
+It will display the following console output:
+
+.. code-block:: console
+
+    *** Booting Zephyr OS build v3.6.0-4569-g483c01ca11a7 ***
+    thread_a: Hello World from cpu 0 on imx95_evk_15x15!
+    thread_b: Hello World from cpu 0 on imx95_evk_15x15!
+    thread_a: Hello World from cpu 0 on imx95_evk_15x15!
+    thread_b: Hello World from cpu 0 on imx95_evk_15x15!
+    thread_a: Hello World from cpu 0 on imx95_evk_15x15!
+
+.. _System Control and Management Interface (SCMI):
+   https://developer.arm.com/documentation/den0056/latest/
+
+.. _i.MX Linux BSP release:
+   https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX
+
+.. _MCUX SDK release:
+   https://mcuxpresso.nxp.com/
+
+References
+==========
+
+More information can refer to NXP official website:
+`NXP website`_.
+
+.. _NXP website:
+   https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors/i-mx-95-applications-processor-family-high-performance-safety-enabled-platform-with-eiq-neutron-npu:iMX95

boards/nxp/imx95_evk_15x15/imx95_evk_15x15-pinctrl.dtsi

@@ -0,0 +1,29 @@
+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/nxp_imx/mimx9596cvtxn-pinctrl.dtsi>
+
+&pinctrl {
+
+	lpuart1_default: lpuart1_default {
+		group0 {
+			pinmux = <&iomuxc_uart1_rxd_lpuart_rx_lpuart1_rx>,
+				<&iomuxc_uart1_txd_lpuart_tx_lpuart1_tx>;
+			bias-pull-up;
+			slew-rate = "slightly_fast";
+			drive-strength = "x4";
+		};
+	};
+
+	lpuart3_default: lpuart3_default {
+		group0 {
+			pinmux = <&iomuxc_gpio_io15_lpuart_rx_lpuart3_rx>,
+				<&iomuxc_gpio_io14_lpuart_tx_lpuart3_tx>;
+			bias-pull-up;
+			slew-rate = "slightly_fast";
+			drive-strength = "x4";
+		};
+	};
+};

boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_a55.dts

@@ -0,0 +1,55 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_mimx95_15x15_a55.dtsi>
+#include "imx95_evk_15x15-pinctrl.dtsi"
+
+/ {
+	model = "NXP i.MX95 15x15 A55";
+	compatible = "fsl,mimx95";
+
+	chosen {
+		zephyr,console = &lpuart1;
+		zephyr,shell-uart = &lpuart1;
+		/* sram node actually locates at DDR DRAM */
+		zephyr,sram = &dram;
+	};
+
+	cpus {
+		cpu@0 {
+			status = "disabled";
+		};
+
+		cpu@100 {
+			status = "disabled";
+		};
+
+		cpu@200 {
+			status = "disabled";
+		};
+
+		cpu@300 {
+			status = "disabled";
+		};
+
+		cpu@400 {
+			status = "disabled";
+		};
+	};
+
+	dram: memory@d0000000 {
+		reg = <0xd0000000 DT_SIZE_M(1)>;
+	};
+};
+
+&lpuart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&lpuart1_default>;
+	pinctrl-names = "default";
+};

boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_a55.yaml

@@ -0,0 +1,18 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: imx95_evk_15x15/mimx9596/a55
+name: NXP i.MX95 15x15 EVK A55
+type: mcu
+arch: arm64
+toolchain:
+  - zephyr
+  - cross-compile
+ram: 1024
+supported:
+  - uart
+  - counter
+vendor: nxp

boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_a55_defconfig

@@ -0,0 +1,35 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ARM Options
+CONFIG_AARCH64_IMAGE_HEADER=y
+CONFIG_ARMV8_A_NS=y
+
+# MMU Options
+CONFIG_MAX_XLAT_TABLES=64
+
+# Cache Options
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_DCACHE_LINE_SIZE_DETECT=y
+CONFIG_ICACHE_LINE_SIZE_DETECT=y
+
+# Zephyr Kernel Configuration
+CONFIG_XIP=n
+CONFIG_KERNEL_DIRECT_MAP=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_CLOCK_CONTROL=y
+
+CONFIG_MBOX=y
+CONFIG_ARM_SCMI=y
+CONFIG_INTC_INIT_PRIORITY=2
+CONFIG_MBOX_INIT_PRIORITY=3