plat: renesas: Add support for RZ/A series

plat/renesas/rza/board/a3m_ek_nor/platform.mk

@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2024-2025, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BOARD 	:= a3m_ek_nor
+
+APPLOAD	?= RZ_NOFIP
+$(eval $(call add_define,APPLOAD))
+
+include plat/renesas/rza/common/rz_common.mk
+
+XSPI0_DEVICE		?=	qspiflash_mx25l25645g
+XSPI_DEVICE_TYPE	:=	QSPI
+$(eval $(call add_define_val,XSPI_DEVICE_TYPE,\"${XSPI_DEVICE_TYPE}\"))
+
+NAND			:=	0
+RZ_FLASH_SIZE		?=	33554432 # 32MB
+$(eval $(call add_define,RZ_FLASH_SIZE))
+
+ifneq (${USE_SDRAM},0)
+ifeq (${DDR_PLL4},1333)
+DDR_SOURCES		+=	plat/renesas/rza/soc/a3m/drivers/ddr/param_mc_C-011_D3-02-1.c	\
+				plat/renesas/rza/common/drivers/ddr/param_swizzle_T1.c
+else
+DDR_PLL4		:= 	1600
+DDR_SOURCES		+=	plat/renesas/rza/soc/a3m/drivers/ddr/param_mc_C-011_D3-01-1.c	\
+				plat/renesas/rza/common/drivers/ddr/param_swizzle_T1.c
+endif
+$(eval $(call add_define,DDR_PLL4))
+endif
+
+include plat/renesas/rza/soc/a3m/rz_xspi.mk
+include plat/renesas/rza/soc/a3m/soc.mk

plat/renesas/rza/board/a3ul_smarc_octal/platform.mk

@@ -0,0 +1,34 @@
+#
+# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BOARD	:= a3ul_smarc_octal
+
+APPLOAD	?= RZ_NOFIP
+$(eval $(call add_define,APPLOAD))
+
+include plat/renesas/rza/common/rz_common.mk
+
+XSPI1_DEVICE		?=	octaflash_mx66uw
+XSPI1_IF_OPTION		?=	.device_size=128*1024*1024
+XSPI2_DEVICE		?=	octaram_apsxx
+XSPI2_IF_OPTION		?=	.device_size=64*1024*1024
+XSPI_DEVICE_TYPE	:=	OCTA
+$(eval $(call add_define_val,XSPI_DEVICE_TYPE,\"${XSPI_DEVICE_TYPE}\"))
+
+NAND			:=	0
+RZ_FLASH_SIZE		?=	134217728 # 128MB
+$(eval $(call add_define,RZ_FLASH_SIZE))
+
+ifneq (${USE_SDRAM},0)
+DDR_SOURCES		+=	plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D4-01-2.c	\
+				plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud2.c
+
+DDR_PLL4		:=	1600
+$(eval $(call add_define,DDR_PLL4))
+endif
+
+include plat/renesas/rza/soc/a3ul/rz_xspi.mk
+include plat/renesas/rza/soc/a3ul/soc.mk

plat/renesas/rza/board/a3ul_smarc_qspi/platform.mk

@@ -0,0 +1,31 @@
+#
+# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BOARD	:= a3ul_smarc_qspi
+
+APPLOAD	?= RZ_NOFIP
+$(eval $(call add_define,APPLOAD))
+
+include plat/renesas/rza/common/rz_common.mk
+
+XSPI0_DEVICE		?= qspiflash_at25
+XSPI_DEVICE_TYPE	:= QSPI
+$(eval $(call add_define_val,XSPI_DEVICE_TYPE,\"${XSPI_DEVICE_TYPE}\"))
+
+NAND			:= 0
+RZ_FLASH_SIZE 		?= 16777216 # 16MB
+$(eval $(call add_define,RZ_FLASH_SIZE))
+
+ifneq (${USE_SDRAM},0)
+DDR_SOURCES		+=	plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D4-01-2.c	\
+				plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud2.c
+
+DDR_PLL4		:= 1600
+$(eval $(call add_define,DDR_PLL4))
+endif
+
+include plat/renesas/rza/soc/a3ul/rz_xspi.mk
+include plat/renesas/rza/soc/a3ul/soc.mk

plat/renesas/rza/common/aarch64/plat_helpers.S

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+
+	.globl	platform_mem_init
+	.globl	plat_my_core_pos
+	.globl	plat_crash_console_init
+	.globl	plat_crash_console_putc
+	.globl	plat_crash_console_flush
+
+func platform_mem_init
+	ret
+endfunc platform_mem_init
+
+func plat_my_core_pos
+	mrs x0, mpidr_el1
+	lsr x0, x0, #MPIDR_AFF1_SHIFT
+	and x0, x0, #MPIDR_CPU_MASK
+	ret
+endfunc plat_my_core_pos
+
+func plat_crash_console_init
+	mov x0, #1
+	ret
+endfunc plat_crash_console_init
+
+func plat_crash_console_putc
+	ret
+endfunc plat_crash_console_putc
+
+func plat_crash_console_flush
+	mov x0, #0
+	ret
+endfunc plat_crash_console_flush

plat/renesas/rza/common/bl2_plat_mem_params_desc.c

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+#include <common/desc_image_load.h>
+
+static bl_mem_params_node_t bl2_mem_params_descs[] = {
+#if (APPLOAD == RZ_NOFIP)
+	{
+		.image_id = MAX_IMAGE_IDS,
+
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+				      entry_point_info_t,
+				      SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.spsr =
+			SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS),
+		.ep_info.pc = BSP_BASE,
+		.ep_info.args.arg0 = (uintptr_t)PARAMS_BASE,
+
+		SET_STATIC_PARAM_HEAD(
+			image_info, PARAM_EP, VERSION_2, image_info_t,
+			IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
+
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	}
+#else
+	{
+#if RZA3
+		.image_id = BL31_IMAGE_ID,
+
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+				      entry_point_info_t,
+				      SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.spsr =
+			SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS),
+		.ep_info.pc = BSP_BASE,
+		.ep_info.args.arg0 = (uintptr_t)PARAMS_BASE,
+
+		SET_STATIC_PARAM_HEAD(
+			image_info, PARAM_EP, VERSION_2, image_info_t,
+			IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
+		.image_info.image_max_size = BSP_LIMIT - BSP_BASE,
+		.image_info.image_base = BSP_BASE,
+
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+#endif /* RZA3 */
+	}
+#endif /* (APPLOAD == RZ_NOFIP) */
+};
+
+REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)

plat/renesas/rza/common/bl2_plat_setup.c

@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <string.h>
+
+#include <plat/common/common_def.h>
+#include <plat_tzc_def.h>
+#include <platform_def.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/desc_image_load.h>
+#include <cpg.h>
+#include <ddr.h>
+#include <drivers/generic_delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_compat.h>
+#include <pfc.h>
+#include <rz_private.h>
+#include <rza_ipl_version.h>
+#include <rza_mmu.h>
+#include <rza_printf.h>
+#include <scifa.h>
+#include <syc.h>
+#include <sys_regs.h>
+
+static console_t console;
+
+int bl2_plat_handle_pre_image_load(unsigned int image_id)
+{
+	return 0;
+}
+
+int bl2_plat_handle_post_image_load(unsigned int image_id)
+{
+	static bl2_to_bl31_params_mem_t *params;
+	bl_mem_params_node_t *bl_mem_params;
+
+	if (!params) {
+		params = (bl2_to_bl31_params_mem_t *)PARAMS_BASE;
+		memset((void *)PARAMS_BASE, 0, sizeof(*params));
+	}
+
+	bl_mem_params = get_bl_mem_params_node(image_id);
+
+	switch (image_id) {
+	case BL32_IMAGE_ID:
+		memcpy(&params->bl32_ep_info, &bl_mem_params->ep_info,
+		       sizeof(entry_point_info_t));
+		break;
+	case BL33_IMAGE_ID:
+		memcpy(&params->bl33_ep_info, &bl_mem_params->ep_info,
+		       sizeof(entry_point_info_t));
+		break;
+	default:
+		/* Do nothing in default case */
+		break;
+	}
+
+	return 0;
+}
+
+void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
+				  u_register_t arg3, u_register_t arg4)
+{
+	int ret;
+
+	/* early setup Clock and Reset */
+	cpg_early_setup();
+
+	/* initialize SYC */
+	syc_init(PLAT_SYC_INCK_HZ);
+
+	/* initialize Timer */
+	generic_delay_timer_init();
+
+	/* setup PFC */
+	pfc_setup();
+
+	/* setup Clock and Reset */
+	cpg_setup();
+
+	/* initialize console driver */
+	ret = console_rza_register(PLAT_SCIF0_BASE, PLAT_UART_INCK_HZ,
+				   PLAT_UART_BARDRATE, &console);
+	if (!ret)
+		panic();
+
+	console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH);
+
+	RZA_PRINTF("Initial Program Loader %s\n", RZA_IPL_VERSION_STRING);
+}
+
+void bl2_el3_plat_arch_setup(void)
+{
+	rza_mmu_pgtbl_cfg_t g_mmu_pagetable_array[] = {
+		/* vaddress, paddress,   size,       attribute */
+		{ 0x00000000, 0x00000000, 0x00200000,
+		  RZA_MMU_ATTRIBUTE_NORMAL_CACHEABLE },
+		{ 0x00200000, 0x00200000, 0x0FE00000,
+		  RZA_MMU_ATTRIBUTE_ACCESS_FAULT },
+		{ 0x10000000, 0x10000000, 0x10000000,
+		  RZA_MMU_ATTRIBUTE_DEVICE },
+		{ 0x20000000, 0x20000000, 0x10000000,
+		  RZA_MMU_ATTRIBUTE_NORMAL_CACHEABLE },
+		{ 0x30000000, 0x30000000, 0x10000000,
+		  RZA_MMU_ATTRIBUTE_ACCESS_FAULT },
+		{ 0x40000000, 0x40000000, 0x40000000,
+		  RZA_MMU_ATTRIBUTE_NORMAL_CACHEABLE },
+		{ 0x80000000, 0x80000000, 0x40000000,
+		  RZA_MMU_ATTRIBUTE_ACCESS_FAULT },
+		{ 0xC0000000, 0xC0000000, 0x40000000,
+		  RZA_MMU_ATTRIBUTE_ACCESS_FAULT },
+		{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+		  RZA_MMU_ATTRIBUTE_CONFIG_END }
+	};
+
+	if (0 != plat_mmu_init(g_mmu_pagetable_array)) {
+		panic();
+	}
+	plat_mmu_enable();
+}
+
+void bl2_platform_setup(void)
+{
+	/* Setup TZC-400, Access Control */
+	plat_security_setup();
+
+#if USE_SDRAM
+	/* initialize DDR */
+	ddr_setup();
+#endif /* DEBUG_FPGA */
+
+	rz_io_setup();
+
+	RZ_RUN_TESTS();
+
+#if (APPLOAD == RZ_NOFIP)
+	rza_load_fsp();
+#endif
+	rza_print_descs();
+}