atualização UART Buffer

peripherals/uart/pll/pll_quartus.cmp

@@ -1,26 +1,26 @@
---Copyright (C) 2020  Intel Corporation. All rights reserved.
---Your use of Intel Corporation's design tools, logic functions 
---and other software and tools, and any partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Intel Program License 
---Subscription Agreement, the Intel Quartus Prime License Agreement,
---the Intel FPGA IP License Agreement, or other applicable license
---agreement, including, without limitation, that your use is for
---the sole purpose of programming logic devices manufactured by
---Intel and sold by Intel or its authorized distributors.  Please
---refer to the applicable agreement for further details, at
---https://fpgasoftware.intel.com/eula.
-
-
-component pll_quartus
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		locked		: OUT STD_LOGIC 
-	);
-end component;
+--Copyright (C) 2020  Intel Corporation. All rights reserved.
+--Your use of Intel Corporation's design tools, logic functions 
+--and other software and tools, and any partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Intel Program License 
+--Subscription Agreement, the Intel Quartus Prime License Agreement,
+--the Intel FPGA IP License Agreement, or other applicable license
+--agreement, including, without limitation, that your use is for
+--the sole purpose of programming logic devices manufactured by
+--Intel and sold by Intel or its authorized distributors.  Please
+--refer to the applicable agreement for further details, at
+--https://fpgasoftware.intel.com/eula.
+
+
+component pll_quartus
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;

peripherals/uart/pll/pll_quartus.ppf

@@ -1,12 +1,12 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<!DOCTYPE pinplan>
-<pinplan intended_family="MAX 10" variation_name="pll_quartus" megafunction_name="ALTPLL" specifies="all_ports">
-<global>
-<pin name="areset" direction="input" scope="external"  />
-<pin name="inclk0" direction="input" scope="external" source="clock"  />
-<pin name="c0" direction="output" scope="external" source="clock"  />
-<pin name="c1" direction="output" scope="external" source="clock"  />
-<pin name="locked" direction="output" scope="external"  />
-
-</global>
-</pinplan>
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="MAX 10" variation_name="pll_quartus" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>

peripherals/uart/pll/pll_quartus.qip

@@ -1,7 +1,7 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "20.1"
-set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_quartus.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus_inst.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus.cmp"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus.ppf"]
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_quartus.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus.ppf"]