Gpio_deb updates (#68)

* Debouncer_files

* debouncer_de10files

* Update README.md

* Criado endereço para o gpio_deb

---------

Co-authored-by: Renan Augusto Starke <[email protected]>

memory/iodatabusmux.vhd

@@ -14,21 +14,22 @@ entity iodatabusmux is
 
     port(
         daddress                : in  unsigned(31 downto 0); --! Connect to RISC-V data bus address 
-        ddata_r_gpio            : in std_logic_vector(31 downto 0);
-        ddata_r_segments        : in std_logic_vector(31 downto 0);
-        ddata_r_uart            : in std_logic_vector(31 downto 0);
-        ddata_r_adc             : in std_logic_vector(31 downto 0);
-        ddata_r_i2c             : in std_logic_vector(31 downto 0);
-        ddata_r_timer           : in std_logic_vector(31 downto 0);
-        ddata_r_dif_fil         : in std_logic_vector(31 downto 0);
-        ddata_r_stepmot         : in std_logic_vector(31 downto 0);
-        ddata_r_lcd             : in std_logic_vector(31 downto 0);
-        ddata_r_nn_accelerator  : in std_logic_vector(31 downto 0);
-        ddata_r_fir_fil         : in std_logic_vector(31 downto 0);
-        ddata_r_spwm            : in std_logic_vector(31 downto 0);
-    	ddata_r_crc		        : in std_logic_vector(31 downto 0);
-        ddata_r_key             : in std_logic_vector(31 downto 0);
-        ddata_r_accelerometer   : in std_logic_vector(31 downto 0);
+
+        ddata_r_gpio            : in  std_logic_vector(31 downto 0);
+        ddata_r_segments        : in  std_logic_vector(31 downto 0);
+        ddata_r_uart            : in  std_logic_vector(31 downto 0);
+        ddata_r_adc             : in  std_logic_vector(31 downto 0);
+        ddata_r_i2c             : in  std_logic_vector(31 downto 0);
+        ddata_r_timer           : in  std_logic_vector(31 downto 0);
+        ddata_r_dif_fil          : in  std_logic_vector(31 downto 0);
+        ddata_r_stepmot         : in  std_logic_vector(31 downto 0);
+        ddata_r_lcd             : in  std_logic_vector(31 downto 0);
+        ddata_r_nn_accelerator  : in   std_logic_vector(31 downto 0);
+        ddata_r_fir_fil           :   in   std_logic_vector(31 downto 0);
+        ddata_r_spwm           :   in   std_logic_vector(31 downto 0);
+        ddata_r_crc		         : in  std_logic_vector(31 downto 0);
+        ddata_r_key        :   in   std_logic_vector(31 downto 0);
+        ddata_r_deb_gpio            : in  std_logic_vector(31 downto 0);
         -- Mux 
         ddata_r_periph   : out std_logic_vector(31 downto 0) --! Connect to data bus mux
     );
@@ -40,21 +41,21 @@ begin
     -- Word address, ignoring least significant 4 bytes
 
     with daddress(19 downto 4) select ddata_r_periph <=
-         ddata_r_gpio when x"0000",
-         ddata_r_segments when x"0001",
-         ddata_r_uart when x"0002",
-         ddata_r_adc when x"0003",
-         ddata_r_i2c when x"0004",
-         ddata_r_timer when x"0005",
-         ddata_r_dif_fil when x"0008",
-         ddata_r_stepmot when x"0009",
-         ddata_r_lcd when x"000A",
-         ddata_r_nn_accelerator when x"000B",
-         ddata_r_fir_fil  when x"000D",
-         ddata_r_key when x"000E",
-	     ddata_r_crc when x"000F",
-         ddata_r_spwm  when x"0011",
-         ddata_r_accelerometer when x"0012",
+        ddata_r_gpio when x"0000",
+        ddata_r_segments when x"0001",
+        ddata_r_uart when x"0002",
+        ddata_r_adc when x"0003",
+        ddata_r_i2c when x"0004",
+        ddata_r_timer when x"0005",
+        ddata_r_dif_fil when x"0008",
+        ddata_r_stepmot when x"0009",
+        ddata_r_lcd when x"000A",
+        ddata_r_nn_accelerator when x"000B",
+        ddata_r_fir_fil  when x"000D",
+        ddata_r_key when x"000E",
+        ddata_r_crc when x"000F",
+        ddata_r_spwm  when x"0011",
+        ddata_r_deb_gpio when x"0012",
         -- Add new io peripherals here
         (others => '0') when others;
 end architecture RTL;

memory/iram_quartus.vhd

@@ -65,8 +65,13 @@ BEGIN
 		byte_size => 8,
 		clock_enable_input_a => "BYPASS",
 		clock_enable_output_a => "BYPASS",
-		init_file => "../../../../software/quartus_blink.hex",
 		intended_device_family => "MAX 10",
+
+		-- Specify here core software binary
+		init_file => "../../software/quartus_blink.hex",
+		-- init_file => "./software/irq/quartus_irq_example.hex",
+		-- init_file => "./software/irq/quartus_irq_example.hex",
+
 		lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=1",
 		lpm_type => "altsyncram",
 		numwords_a => 1024,

peripherals/gpio/README.md

@@ -17,3 +17,7 @@ O *temp.vhd* é responsável por converter um valor para a base decimal e aprese
 A função recebe o valor presente em *ddata_w* e o transforma em um número na base decimal. No caso desse projeto, a leitura é feita usando um conversor analógico-digital (ADC) conectado a um sensor de temperatura (LM35). A função basicamente subtrai 10 do valor da variável *temp* e possui um contador responsável por registrar quantas vezes 10 foi subtraído do valor de *temp*. Se *temp* for menor que 10, o programa sai do loop.
 
 A função retorna o valor do contador e, em seguida, o valor convertido é enviado para outra função responsável por apresentar o valor em decimal no display de 7 segmentos. No arquivo *temp.vhd*, esse componente é utilizado para apresentar a temperatura medida pelo sensor nos displays de 7 segmentos, tanto em graus Celsius como em graus Fahrenheit (por exemplo, 12°C/53°F).
+
+# README GPIO deboucer
+
+O GPIO do debouncer foi integrado ao GPIO do projeto com a finalidade de ser uma escolha ao usuário entre usar um ou outro. Com isso foi acrescentado um endereço no iodata_bus para o gpio_deb

peripherals/gpio/debouncer.vhd

@@ -0,0 +1,79 @@
+-------------------------------------------------------
+--! @file
+--! @brief RISCV Simple GPIO module
+--         RAM mapped general purpose I/O
+
+--! @Todo: Module should mask bytes (Word, half word and byte access)
+--         Daddress shoud be unsgined
+--        
+-------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity debouncer is
+
+    generic (
+        --! Chip selec	
+        SYS_FREQ 		: integer := 1; 			-- em megahertz
+        COUNTT 			: integer := 5				--
+    );
+
+    port(
+        clk : in std_logic;
+        rst : in std_logic;
+
+        -- hardware input/output signals
+        input  : in std_logic;
+        output  : out std_logic
+
+    );
+
+
+end entity debouncer;
+
+architecture RTL_gpio of debouncer is
+    signal max_v : unsigned(31 downto 0);
+begin
+    debouncer: process(clk, rst)
+        variable count: unsigned(31 downto 0);
+    begin
+        if rst = '1' then
+            --output <= '0';
+            --max_v <= to_unsigned(SYS_FREQ*COUNT, max_v'length);
+        else
+            if rising_edge(clk) then
+                if (input = '1') then
+                    if max_v = "00000000000000000000000000000000" then
+                    --output <= '1';
+                    else
+                        max_v <= max_v - 1;
+                    end if;
+                else
+                    --max_v <= to_unsigned(SYS_FREQ*COUNT, max_v'length);
+                    --output <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+    debouncer2: process(clk, rst)
+        variable count: unsigned(2 downto 0);
+        variable vetor: unsigned(7 downto 0);
+    begin
+        if rst = '1' then
+            output <= '0';
+            count := to_unsigned(0, count'length);
+            vetor := to_unsigned(0, vetor'length);
+        else
+            if rising_edge(clk) then
+                vetor(to_integer(count)) := input;
+                count:= count +1;
+                if ((vetor = "11111111") or (vetor = "00000000")) then -- se os ultimos 12 sao iguais
+                    output <= input;
+                end if;
+            end if;
+        end if;
+    end process;
+
+end architecture RTL_gpio;

peripherals/gpio/debouncer.vhd.bak

@@ -0,0 +1,81 @@
+-------------------------------------------------------
+--! @file
+--! @brief RISCV Simple GPIO module
+--         RAM mapped general purpose I/O
+
+--! @Todo: Module should mask bytes (Word, half word and byte access)
+--         Daddress shoud be unsgined
+--        
+-------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity debouncer is
+
+    generic (
+        --! Chip selec	
+        SYS_FREQ 		: integer := 1; 			-- em megahertz
+        COUNT 			: integer := 5				--
+    );
+
+    port(
+        clk : in std_logic;
+        rst : in std_logic;
+
+        -- hardware input/output signals
+        input  : in std_logic;
+        output  : out std_logic
+
+    );
+
+
+end entity debouncer;
+
+architecture RTL_gpio of debouncer is
+    signal max_v : unsigned(31 downto 0);
+begin
+    debouncer: process(clk, rst)
+        variable count: unsigned(31 downto 0);
+    begin
+        if rst = '1' then
+            output <= '0';
+            --max_v <= to_unsigned(SYS_FREQ*COUNT, max_v'length);
+        else
+            if rising_edge(clk) then
+                if (input = '1') then
+                    if max_v = "00000000000000000000000000000000" then
+                    --output <= '1';
+                    else
+                        max_v <= max_v - 1;
+                    end if;
+                else
+                    --max_v <= to_unsigned(SYS_FREQ*COUNT, max_v'length);
+                    --output <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+    debouncer2: process(clk, rst)
+        variable count: unsigned(11 downto 0);
+        variable vetor: unsigned(11 downto 0);
+    begin
+        if rst = '1' then
+            output <= '0';
+            count := to_unsigned(0, count'length);
+        else
+            if rising_edge(clk) then
+                count := count sll 1;
+                vetor := (vetor and (not count));
+                if input = '1' then
+                    vetor := vetor or count;
+                end if;
+                if ((vetor = "111111111111") or (vetor = "000000000000")) then -- se os ultimos 12 sao iguais
+                    output <= input;
+                end if;
+            end if;
+        end if;
+    end process;
+
+end architecture RTL_gpio;

peripherals/gpio/gpio_deb.vhd

@@ -0,0 +1,118 @@
+-------------------------------------------------------
+--! @file
+--! @brief RISCV Simple GPIO module
+--         RAM mapped general purpose I/O
+
+--! @Todo: Module should mask bytes (Word, half word and byte access)
+--         Daddress shoud be unsgined
+--        
+-------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity gpio_deb is
+    generic (
+        --! Chip selec
+        MY_CHIPSELECT : std_logic_vector(1 downto 0) := "10";
+        MY_WORD_ADDRESS : unsigned(15 downto 0) := x"0120"
+    );
+
+    port(
+        clk : in std_logic;
+        rst : in std_logic;
+
+        -- Core data bus signals
+        -- ToDo: daddress shoud be unsgined
+        daddress  : in  unsigned(31 downto 0);
+        ddata_w	  : in 	std_logic_vector(31 downto 0);
+        ddata_r   : out	std_logic_vector(31 downto 0);
+        d_we      : in std_logic;
+        d_rd	  : in std_logic;
+        dcsel	  : in std_logic_vector(1 downto 0);	--! Chip select 
+        -- ToDo: Module should mask bytes (Word, half word and byte access)
+        dmask     : in std_logic_vector(3 downto 0);	--! Byte enable mask 
+
+        -- hardware input/output signals
+        input  : in std_logic_vector(31 downto 0);
+        output : out std_logic_vector(31 downto 0)
+    );
+end entity gpio_deb;
+
+architecture RTL of gpio_deb is
+    signal result : std_logic_vector(31 downto 0);
+
+begin
+    -- Input register
+    process(clk, rst)
+    begin
+        if rst = '1' then
+            ddata_r <= (others => '0');
+        else
+            if rising_edge(clk) then
+                if (d_rd = '1') and (dcsel = MY_CHIPSELECT) then
+                    if daddress(15 downto 0) =(MY_WORD_ADDRESS) then -- GPIO_ADDRESS
+                    ddata_r <= result;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- Output register
+    process(clk, rst)
+    begin
+        if rst = '1' then
+            output <= (others => '0');
+        else
+            if rising_edge(clk) then
+                if (d_we = '1') and (dcsel = MY_CHIPSELECT)then
+                    --if daddress(15 downto 0) =(TIMER_BASE_ADDRESS + x"0000") then -- TIMER_ADDRESS
+                    if daddress(15 downto 0) =(MY_WORD_ADDRESS+x"01") then -- GPIO_ADDRESS				
+                        -- ToDo: Simplify comparators
+                        -- ToDo: Maybe use byte addressing?  
+                        --       x"01" (word addressing) is x"04" (byte addressing)
+                        -- Address comparator when more than one word is mapped here
+                        --if to_unsigned(daddress, 32)(8 downto 0) = MY_WORD_ADDRESS then
+                        --end if;
+                        output <= ddata_w;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    deb2: entity work.debouncer
+        generic map(
+            SYS_FREQ => 1,
+            COUNTT    => 5
+        )
+        port map(
+            clk    => clk,
+            rst    => rst,
+            input  => input(0),
+            output => result(0)
+        );
+
+
+
+
+--    debouncer: for i in 0 to 31 generate
+--        regs: entity work.debouncer
+--            generic map(
+--                SYS_FREQ => 1,
+--                COUNT    => 5
+--            )
+--            port map(
+--                clk    => clk,
+--                rst    => rst,
+--                input  => input(i),
+--                output => result(i)
+--                --input  => input
+--                --output => result
+--            );
+--    end generate;
+    --debouncer2: 
+
+end architecture RTL;