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# Projeto Quartus de10_lite | ||
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------------------------------------------------------- | ||
--! @file | ||
--! @brief RISCV Simple GPIO module | ||
-- RAM mapped general purpose I/O | ||
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--! @Todo: Module should mask bytes (Word, half word and byte access) | ||
-- Daddress shoud be unsgined | ||
-- | ||
------------------------------------------------------- | ||
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
use ieee.numeric_std.all; | ||
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entity debouncer is | ||
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generic ( | ||
--! Chip selec | ||
SYS_FREQ : integer := 1; -- em megahertz | ||
COUNT : integer := 50 -- | ||
); | ||
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port( | ||
clk : in std_logic; | ||
rst : in std_logic; | ||
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-- hardware input/output signals | ||
input : in std_logic; | ||
output : out std_logic | ||
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); | ||
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end entity debouncer; | ||
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architecture RTL_gpio of debouncer is | ||
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signal max_v : unsigned(31 downto 0); | ||
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begin | ||
debouncer: process(clk, rst) | ||
begin | ||
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if rst = '1' then | ||
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output <= '0'; | ||
max_v <= to_unsigned(SYS_FREQ*COUNT, max_v'length); | ||
else | ||
if rising_edge(clk) then | ||
if (input = '1') then | ||
if max_v = "00000000000000000000000000000000" then | ||
output <= '1'; | ||
else | ||
max_v <= max_v - 1; | ||
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end if; | ||
else | ||
max_v <= to_unsigned(SYS_FREQ*COUNT, max_v'length); | ||
output <= '0'; | ||
end if; | ||
end if; | ||
end if; | ||
end process; | ||
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end architecture RTL_gpio; |
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@@ -0,0 +1,95 @@ | ||
------------------------------------------------------- | ||
--! @file | ||
--! @brief RISCV Simple GPIO module | ||
-- RAM mapped general purpose I/O | ||
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--! @Todo: Module should mask bytes (Word, half word and byte access) | ||
-- Daddress shoud be unsgined | ||
-- | ||
------------------------------------------------------- | ||
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
use ieee.numeric_std.all; | ||
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entity gpio_deb is | ||
generic ( | ||
--! Chip selec | ||
MY_CHIPSELECT : std_logic_vector(1 downto 0) := "10"; | ||
MY_WORD_ADDRESS : unsigned(7 downto 0) := x"10" | ||
); | ||
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port( | ||
clk : in std_logic; | ||
rst : in std_logic; | ||
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-- Core data bus signals | ||
-- ToDo: daddress shoud be unsgined | ||
daddress : in natural; | ||
ddata_w : in std_logic_vector(31 downto 0); | ||
ddata_r : out std_logic_vector(31 downto 0); | ||
d_we : in std_logic; | ||
d_rd : in std_logic; | ||
dcsel : in std_logic_vector(1 downto 0); --! Chip select | ||
-- ToDo: Module should mask bytes (Word, half word and byte access) | ||
dmask : in std_logic_vector(3 downto 0); --! Byte enable mask | ||
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-- hardware input/output signals | ||
input : in std_logic_vector(31 downto 0); | ||
output : out std_logic_vector(31 downto 0) | ||
); | ||
end entity gpio_deb; | ||
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architecture RTL of gpio_deb is | ||
signal result : std_logic_vector(31 downto 0); | ||
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begin | ||
-- Input register | ||
process(clk, rst) | ||
begin | ||
if rst = '1' then | ||
ddata_r <= (others => '0'); | ||
else | ||
if rising_edge(clk) then | ||
if (d_rd = '1') and (dcsel = MY_CHIPSELECT) then | ||
ddata_r <= result; | ||
end if; | ||
end if; | ||
end if; | ||
end process; | ||
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-- Output register | ||
process(clk, rst) | ||
begin | ||
if rst = '1' then | ||
output <= (others => '0'); | ||
else | ||
if rising_edge(clk) then | ||
if (d_we = '1') and (dcsel = MY_CHIPSELECT)then | ||
-- ToDo: Simplify comparators | ||
-- ToDo: Maybe use byte addressing? | ||
-- x"01" (word addressing) is x"04" (byte addressing) | ||
-- Address comparator when more than one word is mapped here | ||
--if to_unsigned(daddress, 32)(8 downto 0) = MY_WORD_ADDRESS then | ||
--end if; | ||
output <= ddata_w; | ||
end if; | ||
end if; | ||
end if; | ||
end process; | ||
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debouncer: for i in 0 to 31 generate | ||
regs: entity work.debouncer | ||
generic map( | ||
SYS_FREQ => 10, | ||
COUNT => 50 | ||
) | ||
port map( | ||
clk => clk, | ||
rst => rst, | ||
input => input(i), | ||
output => result(i) | ||
); | ||
end generate; | ||
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end architecture RTL; |
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@@ -0,0 +1,5 @@ | ||
# Projeto Quartus de10_lite | ||
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 | ||
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 |
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