flash bus - update sensibility list in mealy process

xtarke · Sep 20, 2021 · a69355a · a69355a
1 parent da447d1
commit a69355a
Showing 1 changed file with 5 additions and 2 deletions.
diff --git a/peripherals/flash/dummy/flash_bus.vhd b/peripherals/flash/dummy/flash_bus.vhd
@@ -79,7 +79,8 @@ architecture rtl of flash_bus is
     signal memory : reg_array; -- no initialization
 
     -- addr_local will contain the flash word (32-bit) based address without
-    -- offset. i.e. this is the correct address use internally in this component
+    -- offset. i.e. this is the correct address used internally in this
+    -- component
     signal addr_local : unsigned(22 downto 0);
 
   begin
@@ -143,9 +144,11 @@ architecture rtl of flash_bus is
   end process;
 
   -- mealy
-  process (state)
+  process (state, memory, addr_local, ddata_w)
   begin
 
+    -- ddata_r <= (others => '0');
+
     case state is
       when IDLE =>