feat: modifica sint p/ contemplar lcd

.gitignore

@@ -0,0 +1,4 @@
+output_files/
+simulation/
+db/
+incremental_db/

peripherals/lcd_hd44780/sint2/de10_lite/de0_lite.vhd

@@ -120,6 +120,7 @@ architecture rtl of de0_lite is
     signal ddata_r_i2c : std_logic_vector(31 downto 0);
     signal ddata_r_dig_fil : std_logic_vector(31 downto 0);
     signal ddata_r_stepmot : std_logic_vector(31 downto 0);
+		signal ddata_r_hd44780 : std_logic_vector(31 downto 0);
 
 	 signal data_in_dig_fil : std_logic_vector(15 downto 0);
 
@@ -297,6 +298,43 @@ begin
             hex6     => open,
             hex7     => open
         );
+
+		lcd : entity work.lcd_hd44780
+				port map(
+					clk            => clk_1k,
+					rst            => SW(9),
+					--
+					daddress => daddress,
+					ddata_w  => ddata_w,
+					ddata_r  => ddata_r_segments,
+					d_we     => d_we,
+					d_rd     => d_rd,
+					dcsel    => dcsel,
+					dmask    => dmask,
+					--
+					lcd_data(7)    => ARDUINO_IO(0),
+					lcd_data(6)    => ARDUINO_IO(1),
+					lcd_data(5)    => ARDUINO_IO(2),
+					lcd_data(4)    => ARDUINO_IO(3),
+					lcd_data(3)    => ARDUINO_IO(4),
+					lcd_data(2)    => ARDUINO_IO(5),
+					lcd_data(1)    => ARDUINO_IO(6),
+					lcd_data(0)    => ARDUINO_IO(7),
+					lcd_rs         => ARDUINO_IO(9),
+					lcd_e          => ARDUINO_IO(8),
+					lcd_is_busy    => LEDR(8)
+				);		
+
+        -- daddress    : in  unsigned(DADDRESS_BUS_SIZE - 1 downto 0);
+        -- ddata_w     : in  std_logic_vector(31 downto 0);
+        -- ddata_r     : out std_logic_vector(31 downto 0);
+        -- d_we        : in  std_logic;
+        -- d_rd        : in  std_logic;
+        -- dcsel       : in  std_logic_vector(1 downto 0); --! Chip select 
+        -- -- ToDo: Module should mask bytes (Word, half word and byte access)
+        -- dmask       : in  std_logic_vector(3 downto 0); --! Byte enable mask				
+
+
 
 	-- Connect input hardware to gpio data
 	gpio_input(3 downto 0) <= SW(3 downto 0);

peripherals/lcd_hd44780/sint2/de10_lite/de10_lite.qsf

@@ -216,7 +216,6 @@ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
 
 set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 set_global_assignment -name VHDL_FILE ../../lcd_hd44780.vhd
 set_global_assignment -name VHDL_FILE ../../../gpio/gpio.vhd
 set_global_assignment -name VHDL_FILE ../../../gpio/led_displays.vhd
@@ -242,4 +241,5 @@ set_global_assignment -name VHDL_FILE ../../../../alu/alu_types.vhd
 set_global_assignment -name VHDL_FILE ../../../../alu/alu.vhd
 set_global_assignment -name VHDL_FILE de0_lite.vhd
 set_global_assignment -name QIP_FILE pll.qip
-set_global_assignment -name SOURCE_FILE db/de10_lite.cmp.rdb
+set_global_assignment -name SOURCE_FILE db/de10_lite.cmp.rdb
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top