Added peripherals

CONTRIBUTORS.md

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+RISVC contributors (sorted alphabetically)
+============================================
+
+* **[Cleisson Fernandes Da Silva](https://github.com/cleissom)**
+
+  * SDRAM firts integration (first attempt)
+
+* **[Ian Schmiegelow Dannapel](https://github.com/Eximmius)**
+
+  * VGA integration (internal SRAM)
+
+* **[Jeferson Cansi Pedroso](https://github.com/jefersonpedroso)**
+
+  * MAX10 ADC integration
+
+* **[Lucas Seara Manoel](https://github.com/lsmanoel)**
+
+  * [M] Instructions extension.
+
+* **[Marcos Vinicius Leal Da Silva](https://github.com/marcosleal)**
+
+  * 9600 baud rate UART.
+

alu/m/M.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.M_types.all;
+
+entity M is
+	port(
+		M_data : in M_data_t;		
+		dataOut  : out std_logic_vector(31 downto 0)
+	);
+end entity;
+
+architecture RTL of M is
+	-------------------------------------------------------------------	
+
+
+	signal mul_signed: Signed(63 downto 0);
+	signal mulu_unsigned: Unsigned(63 downto 0);
+
+	signal div_signed: Signed(31 downto 0);
+	signal divu_unsigned: Unsigned(31 downto 0);
+
+	signal rem_signed: Signed(31 downto 0);
+	signal remu_unsigned: Unsigned(31 downto 0);
+
+begin
+	--===============================================================--
+
+	mul_signed <= M_data.a*M_data.b;
+	mulu_unsigned <= Unsigned(M_data.a)*Unsigned(M_data.b);
+
+	div_signed <= M_data.a/M_data.b;
+	divu_unsigned <= Unsigned(M_data.a)/Unsigned(M_data.b);
+
+	rem_signed <= M_data.a mod M_data.b;  
+	remu_unsigned <= Unsigned(M_data.a) mod Unsigned(M_data.b);
+
+	ula_op : with M_data.code select
+		dataOut <=	Std_logic_vector(mul_signed(31 downto 0)) when M_MUL,
+					Std_logic_vector(mul_signed(63 downto 32)) when M_MULH,
+
+					Std_logic_vector(mulu_unsigned(63 downto 32)) when M_MULHU,
+					Std_logic_vector(mulu_unsigned(63 downto 32)) when M_MULHSU,
+
+					Std_logic_vector(div_signed) when M_DIV,
+					Std_logic_vector(divu_unsigned) when M_DIVU,
+
+					Std_logic_vector(rem_signed) when M_REM,
+					Std_logic_vector(remu_unsigned) when M_REMU,
+
+			        (others => '0') when others;
+
+end architecture;

alu/m/M_types.vhd

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+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package M_types is
+
+	--! Record for instruction decoding
+	type M_data_t is record
+		a : signed(31 downto 0);	--! Source operand A
+		b : signed(31 downto 0);	--! Source operand B
+		code  : std_logic_vector(2 downto 0);	--! Alu operation code
+	end record M_data_t;
+
+	constant M_MUL: std_logic_vector(2 downto 0) :=	 	"000";
+	constant M_MULH: std_logic_vector(2 downto 0) := 	"001";
+	constant M_MULHU: std_logic_vector(2 downto 0) := 	"010";
+	constant M_MULHSU: std_logic_vector(2 downto 0) := 	"011";		
+	constant M_DIV: std_logic_vector(2 downto 0) :=	  	"100";
+	constant M_DIVU: std_logic_vector(2 downto 0) := 	"101";
+	constant M_REM: std_logic_vector(2 downto 0) :=	  	"110";
+	constant M_REMU: std_logic_vector(2 downto 0) := 	"111";
+
+end package;
+
+package body M_types is
+
+end;

alu/m/README.md

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+# [“M” Standard Extension for Integer Multiplication and Division, Version 2.0](https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf#chapter.6)
+
+[RV32/64G Instruction Set Listings](https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf#chapter.19)
+
+![M word](./img/M_word.png)
+
+![RV32M Standard Extension](./img/rv32M_standard_extension.png)
+
+* MUL - **Signed\*Signed** 32 bits multiplication (rs1*rs2) - Place lower 32 bits in rd.
+* MULH - **Signed\*Signed** 32 bits multiplication (rs1*rs2) - Place higher 32 bits in rd.
+* MULHU - **Unsigned\*Unsigned** 32 bits multiplication (rs1*rs2) - Place higher 32 bits in rd.
+* MULHSU - **Signed\*Unsigned** 32 bits multiplication (rs1*rs2) - Place higher 32 bits in rd.
+* DIV - **Signed\*Signed** 32 bits division (rs1*rs2) - Place lower 32 bits in rd.
+* DIVU - **Unsigned\*Unsigned** 32 bits division (rs1*rs2) - Place lower 32 bits in rd.
+* REM - **Signed** remainder of the corresponding division operation
+* REMU - **Unsigned** remainder of the corresponding division operation
+
+![RV32M Standard Extension](./img/M_unit.png)
+
+##Files to use M unit:
+
+* M_types.vhd
+* M.vhd
+
+##Testbench:
+
+* tb_M.do - Modelsim
+* tb_M.vhd
+
+##Code to Teste:
+```C
+#include "utils.h"
+#include "hardware.h"
+#include <limits.h>
+
+int main(){
+	volatile int a_int32=3, b_int32=2;
+	volatile int a_int64=3, b_int64=2;
+
+	volatile uint32_t a_uint32=INT_MAX, b_uint32=2;
+	volatile uint64_t a_uint64=INT_MAX, b_uint64=2;
+
+	volatile uint64_t mul_result;
+   	volatile uint32_t mulh_result;
+   	volatile uint32_t mulhsu_result;
+   	volatile uint32_t mulhu_result;
+   	volatile int div_result;
+   	volatile uint32_t divu_result;
+   	volatile int rem_result;
+   	volatile uint32_t remu_result;
+
+	while (1){
+
+
+		mul_result = a_uint32 * b_int32;
+
+		mulh_result = a_int64*b_int64;
+
+		mulhsu_result = a_uint64*b_uint64;
+
+		mulh_result = a_int64*b_int64;
+
+		div_result = a_int32/b_int32;
+
+		divu_result = a_uint32/b_uint32;
+
+		div_result = a_int32%b_int32;
+
+		divu_result = a_uint32%b_uint32;
+	}
+
+	return 0;
+}
+```

alu/m/tb_M.do

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+#Cria Biblioteca
+vlib work
+
+#Compila Projeto
+vcom M_types.vhd
+vcom M.vhd
+vcom tb_M.vhd
+
+#Simula
+vsim -t ns work.tb_M
+
+#Mosta forma de onda
+view wave
+
+#Adiciona ondas específicas
+#radix: binary, hex, dec
+#label: nome da forma de onda
+
+#------------------------------------------------------------------------------------------
+add wave -radix dec -label a_integer /a_integer
+add wave -radix dec -label b_integer /b_integer
+add wave -radix dec -label M_data_out_integer /M_data_out_integer
+add wave -radix bin -label code_logic_vector /code_logic_vector
+
+#------------------------------------------------------------------------------------------
+run 100ns
+
+wave zoomfull
+write wave wave.pss

alu/m/tb_M.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.M_types.all;
+
+entity tb_M is
+end entity;
+
+architecture waveform of tb_M is
+	-------------------------------------------------------------------
+	-- CLOCK
+	signal clock_50_0_logic, clock_50_PI_logic: std_logic;
+
+	-------------------------------------------------------------------
+	-- M
+	component M is
+		port(
+			M_DATA : in M_data_t;		
+			DATAOUT  : out std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	--------------------------------------------------------------------
+	-- A and B
+	signal a_integer: integer; 
+	signal a_signed: signed (31 downto 0);
+	signal a_logic_vector: std_logic_vector (31 downto 0);
+
+	signal b_integer: integer; 
+	signal b_signed: signed (31 downto 0);
+	signal b_logic_vector: std_logic_vector (31 downto 0);
+
+	--------------------------------------------------------------------
+	-- code
+	signal code_logic_vector: std_logic_vector (2 downto 0);
+
+	--------------------------------------------------------------------
+	-- M_data
+	signal M_data_record: M_data_t;
+
+	--------------------------------------------------------------------
+	-- DATAOUT
+	signal M_data_out_integer: integer;
+	signal M_data_out_signed: signed(31 downto 0);
+	signal M_data_out_logic_vector: std_logic_vector(31 downto 0);
+
+begin
+	--===============================================================--
+	-- M
+	M_vhd: M
+		port map(
+			M_DATA => M_data_record,
+			DATAOUT => M_data_out_logic_vector
+		);
+
+	--===============================================================--
+	-- A and B
+	a_signed <= To_signed(a_integer, 32);
+	a_logic_vector <= Std_logic_vector(a_signed);
+
+	b_signed <= To_signed(b_integer, 32);
+	b_logic_vector <= Std_logic_vector(b_signed);
+
+	a_integer <= 7;
+	b_integer <= 3;
+
+	--===============================================================--
+	-- code 
+	SET_CODE: process -- 50 MHz phase pi
+	begin
+		code_logic_vector <= "000";
+		wait for 10 ns;
+		code_logic_vector <= "001";
+		wait for 10 ns;
+		code_logic_vector <= "010";
+		wait for 10 ns;
+		code_logic_vector <= "011";
+		wait for 10 ns;
+		code_logic_vector <= "100";
+		wait for 10 ns;
+		code_logic_vector <= "101";
+		wait for 10 ns;
+		code_logic_vector <= "110";
+		wait for 10 ns;
+		code_logic_vector <= "111";
+		wait for 10 ns;
+	end process;	
+
+
+	--===============================================================--
+	-- M_data
+	M_data_record.a	<= a_signed;
+	M_data_record.b	<= b_signed;
+	M_data_record.code <= code_logic_vector;
+
+	--===============================================================--
+	-- DATAOUT
+	M_data_out_signed <= Signed(M_data_out_logic_vector);
+	M_data_out_integer <= To_integer(M_data_out_signed);
+
+	--&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&--
+	-- Code
+	M_data_record.code <= code_logic_vector;	
+
+end architecture;

peripherals/README.md

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+# Peripherals base folder

peripherals/adc/README.md

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+
+
+DOCUMENTAÇÃO ADC E DISPLAY 7 SEGMENTOS DE-10LITE
+
+
+1- O HARDWARE
+
+
+A implementação do ADC trata-se de um bloco IP da Altera, é configurado pelo arquivo "adc_qsys.qsys" utilizando-se a ferramenta própria da Altera.
+Maiores informações em https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/archives/ug-m10-adc-16.1.pdf
+
+No arquivo "Top-level Hierarchy", "de0_lite.vhd", pode-se observar a Instancia do Componente ADC bem como o Port Map e Sinais necessários para o seu funcionamento.
+
+No process "-- Output register" o softcore envia ao hardware o número do canal que deve ser lido o ADC e também o registrador com os dígitos separados em hexadecimal que devem ser enviados aos displays de 7 segmentos do kit.
+
+No process "-- Input register" envia-se o valor do ADC para o registrador de I/O do softcore, onde os 12 bits menos significativos do registrador de I/O recebe o valor bruto do ADC e os bits 12 a 15 recebem o número do canal cujo valor foi lido, conforme ilustrado abaixo:
+
+					input_in(11 downto 0) <= adc_sample_data;
+					input_in(15 downto 12) <= cur_adc_ch(3 downto 0);
+					
+
+Também neste mesmo arquivo foi declarado os componentes "displays()" que são responsáveis por receber um dígito hexadecimal e codifiar para os respectivos displays de 7 segmentos presentes no Kit DE-10LITE.
+
+
+2- SOFTWARE
+
+No arquivo "hardware.h" estão definidos os nomes e endereços dos registradores de I/O:
+
+INDATA_ADC -> recebe o valor do ADC e respectivo canal.
+SEL_CH_ADC -> envia ao hardware o número do canal ADC a ser lido
+OUT_SEGS -> envia os dvalores em hexadecimal aos displays de 7 segmentos. São 6 displays ordenados nos 24bits mais significativos.
+
+
+No arquivo "hardware_ADC_7SEG.h" estão definidos uma estrutura de dados para armazenar o valor lido do ADC e seu respectivo canal, bem como a declaração das funções para ler o ADC e escrever nos displays de 7 segmentos.
+
+
+3- Valor ADC.
+
+O valor lido do ADC é bruto, devendo-se fazer as devidas conversões de acordo com a conveniencia pretendida.
+No exemplo do arquivo "firmware.c" o valor foi convertido em mV.
+