atualizado

CONTRIBUTORS.md

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+RISVC contributors (sorted alphabetically)
+============================================
+
+* **[Cleisson Fernandes Da Silva](https://github.com/cleissom)**
+
+  * SDRAM integration (first attempt)
+
+* **[Ian Schmiegelow Dannapel](https://github.com/Eximmius)**
+
+  * VGA integration (internal SRAM)
+
+* **[Jeferson Cansi Pedroso](https://github.com/jefersonpedroso)**
+
+  * MAX10 ADC integration
+
+* **[Lucas Seara Manoel](https://github.com/lsmanoel)**
+
+  * [M] Instructions extension.
+
+* **[Marcos Vinicius Leal Da Silva](https://github.com/marcosleal)**
+
+  * 9600 baud rate UART.
+

README.md

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+# RISC SoftCore
+---
+
+RISC SoftCore é uma implementação em VHDL com fins diádicos do conjunto de instruções RISCV RV32I. Essa versão particular não implementa um pipeline. A ideia é criar um microcontrolador com periféricos comuns como I2C, USART, SPI e GPIOs inicialmente utilizado para disciplina de Dispositivos Lógicos Programáveis.
+
+Ferramentas de programação podem ser obtidas no [RISC-V Website](https://riscv.org/software-status/).
+
+## Getting Started (hardware):
+
+- Simulação:
+    - ModelSim: execução do script testbench.do
+    - testbench: ./core/testbench.vhd
+    - Utilizar uma memória SRAM IP (32-bits x 1024 words):
+        - Quartus RAM: catálogo de IPS, RAM 1-port
+        - Na aba de confguração  __Regs/Clken/Byte Enable/AClrs__, desabilite __'q' output port__ e habilite __Create byte enable for port A__
+        - Na aba de configuração __Mem Init__, habilite e configure o arquivo de inicialização da memória de instruções para __quartus.hex__
+        - Na aba de configuração __Mem Init__, habilite Allow In-System Memory Content Editor.
+    - Se necessário, altere o caminho do arquivo de inicialização de memória (__quartus.hex__) no arquivo iram_quartus.vhdl
+
+- Síntese: Quartus 15 ou superior (testado no Kit de desenvolvimento DE10-Lite)
+    - Projeto: utilize ./sint/de10_lite
+    - Para gravação do programa pós síntese:
+        - Utilizar uma memória SRAM IP (32-bits x 1024 words Quartus RAM
+        - Gravação pelo Tools -> In-System Memory Editor
+    - Utilize uma PLL para ajuste do clock
+
+## Getting Started (software):
+
+A compilação de programas necessita do _toolchain_ __riscv32-unknown-elf__ suportando o subconjunto RV32I. Em ./tests/ há um exemplo bem simples de Makefile. Perceba que na fase atual do projeto utilizamos um _script_ de _linker_ customizado (sections.ld). libc ainda não foi testado/suportado.
+
+### Instalação do compilador no Linux
+
+Guia para instalação no [gnu-mcu-eclipse.github.io](https://gnu-mcu-eclipse.github.io/toolchain/riscv/install/#gnulinux)
+
+Toolchain Release: riscv-none-gcc [Github](https://github.com/gnu-mcu-eclipse/riscv-none-gcc/releases).
+
+1. Atualizar Makefile com o diretório da toolchain. 
+
+Exemplo:
+
+```RISCV_TOOLS_PREFIX = /home/lucas/ssd2/vhdl/softcore/gnu-mcu-riscv/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.2-20190521-0004/bin/riscv32-unknown-elf-```
+
+2. Para compilar, _make_.
+
+### Instalação do compilador no Windows (Windows Subsystem for Linux)
+
+1. Instalar o WSL: [Microsoft Docs](https://docs.microsoft.com/en-us/windows/wsl/install-win10)
+2. Instalar o Ubuntu no WSL
+
+	- Para integrar o Visual Code com o compilador interno ao WSL, siga esse [link](https://devblogs.microsoft.com/commandline/an-in-depth-tutorial-on-linux-development-on-windows-with-wsl-and-visual-studio-code/)
+
+3. No shell Ubuntu (busque Ubuntu no Iniciar do Windows):
+4. Instalar os pacotes para o nodejs:
+
+```sudo apt update
+sudo apt upgrade
+sudo apt install nodejs
+sudo apt install npm
+sudo npm --global install xpm
+```
+
+5. Instalar por xmp [GNU Eclipse](https://gnu-mcu-eclipse.github.io/toolchain/riscv/install/):
+
+```xpm install --global @gnu-mcu-eclipse/riscv-none-gcc```
+
+6. Altere o caminho do compilador no _Makefile_:
+	- de:
+```RISCV_TOOLS_PREFIX = riscv32-unknown-elf-```
+	- para:
+```RISCV_TOOLS_PREFIX = ~/opt/xPacks/@<versão compilador>/.contents/bin/riscv-none-embed-```
+
+7. Utilizando o shell Ubuntu,  mude o diretório atual para o repositório:
+
+```cd /mnt/c/<caminho sistema arquivos Windows>```
+
+8. Para compilar, _make_.
+
+Após a compilação, mova, copie ou faça um _link_ simbólico de ./tests/quartus.hex para a raiz do projeto.
+
+## Simulador Assembly:
+
+RISV baseado no MARS: [RARS](https://github.com/TheThirdOne/rars)

alu/alu.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.alu_types.all;
+
+entity ULA is
+	port(
+		alu_data : in alu_data_t;		
+		dataOut  : out signed(31 downto 0)
+	);
+end entity ULA;
+
+architecture RTL of ULA is
+	signal shamt : std_logic_vector(4 downto 0);
+	signal comp_l  : std_logic_vector(31 downto 0);
+	signal comp_lu  : std_logic_vector(31 downto 0);
+
+	signal or_vector : std_logic_vector(31 downto 0);
+	signal xor_vector : std_logic_vector(31 downto 0);
+	signal and_vector : std_logic_vector(31 downto 0);
+
+begin
+	-- shamt <= std_logic_vector(to_signed(alu_data.b,5));  -- to_unsigned
+	shamt <= std_logic_vector(alu_data.b(4 downto 0));  -- to_unsigned
+
+	comp_l <= x"00000001" when alu_data.a < alu_data.b else (others => '0');
+	--comp_lu <= "1" when (to_unsigned(alu_data.a,32)) < (to_unsigned(alu_data.a,32)) else
+	--	      "0";
+	comp_lu <= x"00000001" when (unsigned(alu_data.a) < unsigned(alu_data.a)) else (others => '0');
+
+	--or_vector <= std_logic_vector(to_signed(alu_data.a,32)) or std_logic_vector(to_signed(alu_data.b,32));
+	or_vector <= std_logic_vector(alu_data.a or alu_data.b);
+	-- xor_vector <= std_logic_vector(to_signed(alu_data.a,32)) xor std_logic_vector(to_signed(alu_data.b,32));
+	xor_vector <= std_logic_vector(alu_data.a xor alu_data.b);
+	-- and_vector <= std_logic_vector(to_signed(alu_data.a,32)) and std_logic_vector(to_signed(alu_data.b,32));
+	and_vector <= std_logic_vector(alu_data.a and alu_data.b);
+
+
+	ula_op : with alu_data.code select
+	dataOut <=	alu_data.a + alu_data.b when ALU_ADD,
+				alu_data.a - alu_data.b when ALU_SUB,				
+				alu_data.a sll to_integer(unsigned(shamt)) when ALU_SLL,
+				signed(comp_l) when ALU_SLT,
+				signed(comp_lu) when ALU_SLTU,				
+				signed(xor_vector)  when ALU_XOR,
+				alu_data.a srl to_integer(unsigned(shamt)) when ALU_SRL,
+				alu_data.a srl to_integer(unsigned(shamt)) when ALU_SRA,
+				signed(or_vector)  when ALU_OR,	
+				signed(and_vector)  when ALU_AND,
+		        (others => '0') when others;
+
+end architecture RTL;

alu/alu_types.vhd

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+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package alu_types is
+
+	--! Record for instruction decoding
+	type alu_data_t is record
+		a : signed(31 downto 0);	--! Source operand A
+		b : signed(31 downto 0);	--! Source operand B
+		code  : std_logic_vector(3 downto 0);	--! Alu operation code
+	end record alu_data_t;
+
+	constant ALU_ADD	: std_logic_vector(3 downto 0) := "0000";
+	constant ALU_SUB	: std_logic_vector(3 downto 0) := "0001";
+
+	constant ALU_SLL	: std_logic_vector(3 downto 0) := "0010";
+	constant ALU_SRL	: std_logic_vector(3 downto 0) := "0011";
+	constant ALU_SRA	: std_logic_vector(3 downto 0) := "0100";
+
+	constant ALU_SLT	: std_logic_vector(3 downto 0) := "0101";
+	constant ALU_SLTU	: std_logic_vector(3 downto 0) := "0111";
+
+	constant ALU_XOR	: std_logic_vector(3 downto 0) := "1000";
+	constant ALU_OR  	: std_logic_vector(3 downto 0) := "1001";
+	constant ALU_AND  	: std_logic_vector(3 downto 0) := "1010";
+
+	constant MUL_ULA 	: std_logic_vector(2 downto 0) := "001";
+	constant AND_ULA 	: std_logic_vector(2 downto 0) := "010";
+	constant OR_ULA 	: std_logic_vector(2 downto 0) := "011";
+	constant XOR_ULA 	: std_logic_vector(2 downto 0) := "100";
+	constant NOT_ULA 	: std_logic_vector(2 downto 0) := "101";
+	constant SLL_ULA 	: std_logic_vector(2 downto 0) := "110";
+	constant SRL_ULA 	: std_logic_vector(2 downto 0) := "111";
+
+	constant MUX_ULA_R		: std_logic_vector(1 downto 0) := "00";
+	constant MUX_ULA_I  	: std_logic_vector(1 downto 0) := "01";
+	constant MUX_ULA_Shift 	: std_logic_vector(1 downto 0) := "10";
+	constant MUX_ULA_BRANCH : std_logic_vector(1 downto 0) := "11";
+
+	constant MUX_BR_ULA		: std_logic := '0';
+	constant MUX_BR_RAM		: std_logic := '1';
+
+	constant MUX_COMP_0		: std_logic := '0';
+	constant MUX_COMP_EQUAL	: std_logic := '1';
+
+	constant PC_DT_PSEUDO 	: std_logic := '0';
+	constant PC_DT_BRANCH	: std_logic := '1';	
+
+	constant LED_IO_REG : std_logic_vector(7 downto 0) := "10000000";
+	constant SW_IO_REG  : std_logic_vector(7 downto 0) := "10000001";
+	constant SEG7_IO_REG: std_logic_vector(7 downto 0) := "10000010";	
+
+end package alu_types;
+
+package body alu_types is
+
+end package body alu_types;

alu/m/M.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.M_types.all;
+
+entity M is
+	port(
+		M_data : in M_data_t;		
+		dataOut  : out std_logic_vector(31 downto 0)
+	);
+end entity;
+
+architecture RTL of M is
+	-------------------------------------------------------------------	
+
+
+	signal mul_signed: Signed(63 downto 0);
+	signal mulu_unsigned: Unsigned(63 downto 0);
+
+	signal div_signed: Signed(31 downto 0);
+	signal divu_unsigned: Unsigned(31 downto 0);
+
+	signal rem_signed: Signed(31 downto 0);
+	signal remu_unsigned: Unsigned(31 downto 0);
+
+begin
+	--===============================================================--
+
+	mul_signed <= M_data.a*M_data.b;
+	mulu_unsigned <= Unsigned(M_data.a)*Unsigned(M_data.b);
+
+	div_signed <= M_data.a/M_data.b;
+	divu_unsigned <= Unsigned(M_data.a)/Unsigned(M_data.b);
+
+	rem_signed <= M_data.a mod M_data.b;  
+	remu_unsigned <= Unsigned(M_data.a) mod Unsigned(M_data.b);
+
+	ula_op : with M_data.code select
+		dataOut <=	Std_logic_vector(mul_signed(31 downto 0)) when M_MUL,
+					Std_logic_vector(mul_signed(63 downto 32)) when M_MULH,
+
+					Std_logic_vector(mulu_unsigned(63 downto 32)) when M_MULHU,
+					Std_logic_vector(mulu_unsigned(63 downto 32)) when M_MULHSU,
+
+					Std_logic_vector(div_signed) when M_DIV,
+					Std_logic_vector(divu_unsigned) when M_DIVU,
+
+					Std_logic_vector(rem_signed) when M_REM,
+					Std_logic_vector(remu_unsigned) when M_REMU,
+
+			        (others => '0') when others;
+
+end architecture;

alu/m/M_types.vhd

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+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package M_types is
+
+	--! Record for instruction decoding
+	type M_data_t is record
+		a : signed(31 downto 0);	--! Source operand A
+		b : signed(31 downto 0);	--! Source operand B
+		code  : std_logic_vector(2 downto 0);	--! Alu operation code
+	end record M_data_t;
+
+	constant M_MUL: std_logic_vector(2 downto 0) :=	 	"000";
+	constant M_MULH: std_logic_vector(2 downto 0) := 	"001";
+	constant M_MULHU: std_logic_vector(2 downto 0) := 	"010";
+	constant M_MULHSU: std_logic_vector(2 downto 0) := 	"011";		
+	constant M_DIV: std_logic_vector(2 downto 0) :=	  	"100";
+	constant M_DIVU: std_logic_vector(2 downto 0) := 	"101";
+	constant M_REM: std_logic_vector(2 downto 0) :=	  	"110";
+	constant M_REMU: std_logic_vector(2 downto 0) := 	"111";
+
+end package;
+
+package body M_types is
+
+end;

alu/m/README.md

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+# [“M” Standard Extension for Integer Multiplication and Division, Version 2.0](https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf#chapter.6)
+
+[RV32/64G Instruction Set Listings](https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf#chapter.19)
+
+![M word](./img/M_word.png)
+
+![RV32M Standard Extension](./img/rv32M_standard_extension.png)
+
+* MUL - **Signed\*Signed** 32 bits multiplication (rs1*rs2) - Place lower 32 bits in rd.
+* MULH - **Signed\*Signed** 32 bits multiplication (rs1*rs2) - Place higher 32 bits in rd.
+* MULHU - **Unsigned\*Unsigned** 32 bits multiplication (rs1*rs2) - Place higher 32 bits in rd.
+* MULHSU - **Signed\*Unsigned** 32 bits multiplication (rs1*rs2) - Place higher 32 bits in rd.
+* DIV - **Signed\*Signed** 32 bits division (rs1*rs2) - Place lower 32 bits in rd.
+* DIVU - **Unsigned\*Unsigned** 32 bits division (rs1*rs2) - Place lower 32 bits in rd.
+* REM - **Signed** remainder of the corresponding division operation
+* REMU - **Unsigned** remainder of the corresponding division operation
+
+![RV32M Standard Extension](./img/M_unit.png)
+
+##Files to use M unit:
+
+* M_types.vhd
+* M.vhd
+
+##Testbench:
+
+* tb_M.do - Modelsim
+* tb_M.vhd
+
+##Code to Teste:
+```C
+#include "utils.h"
+#include "hardware.h"
+#include <limits.h>
+
+int main(){
+	volatile int a_int32=3, b_int32=2;
+	volatile int a_int64=3, b_int64=2;
+
+	volatile uint32_t a_uint32=INT_MAX, b_uint32=2;
+	volatile uint64_t a_uint64=INT_MAX, b_uint64=2;
+
+	volatile uint64_t mul_result;
+   	volatile uint32_t mulh_result;
+   	volatile uint32_t mulhsu_result;
+   	volatile uint32_t mulhu_result;
+   	volatile int div_result;
+   	volatile uint32_t divu_result;
+   	volatile int rem_result;
+   	volatile uint32_t remu_result;
+
+	while (1){
+
+
+		mul_result = a_uint32 * b_int32;
+
+		mulh_result = a_int64*b_int64;
+
+		mulhsu_result = a_uint64*b_uint64;
+
+		mulh_result = a_int64*b_int64;
+
+		div_result = a_int32/b_int32;
+
+		divu_result = a_uint32/b_uint32;
+
+		div_result = a_int32%b_int32;
+
+		divu_result = a_uint32%b_uint32;
+	}
+
+	return 0;
+}
+```