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Merge pull request #21 from luscasos/master
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making SDRAM work
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@xtarke
xtarke authored Oct 14, 2020
2 parents 3c84ce9 + 6f0427b commit 1446e13
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Showing 7 changed files with 151 additions and 188 deletions.
5 changes: 5 additions & 0 deletions memory/databusmux.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,8 @@ entity databusmux is
idata : in std_logic_vector(31 downto 0);
ddata_r_mem : in std_logic_vector(31 downto 0);
ddata_r_gpio: in std_logic_vector(31 downto 0);
ddata_r_sdram: in std_logic_vector(31 downto 0);


-- Mux
ddata_r : out std_logic_vector(31 downto 0)
Expand All @@ -30,10 +32,13 @@ begin
-- 0x00000 -> Instruction memory
-- 0x20000 -> Data memory
-- 0x40000 -> Input/Output generic address space
-- 0x60000 -> SDRAM

with dcsel select
ddata_r <= idata when "00",
ddata_r_mem when "01",
ddata_r_gpio when "10",
ddata_r_sdram when "11",
(others => '0') when others;

end architecture RTL;
2 changes: 1 addition & 1 deletion peripherals/gpio/sint/de10_lite/de10_lite.qsf
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Expand Up @@ -42,7 +42,7 @@ set_global_assignment -name DEVICE 10M50DAF484C7G
set_global_assignment -name TOP_LEVEL_ENTITY de0_lite
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:49:34 JUNE 20, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
Expand Down
197 changes: 59 additions & 138 deletions peripherals/sdram/de10_lite.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -70,11 +70,9 @@ architecture rtl of de10_lite is

signal clk : std_logic;
signal clk_sdram_ctrl : std_logic;
signal clk_sdram_chip : std_logic;
signal clk_vga : std_logic;


signal rst : std_logic;
signal rst_n : std_logic;

-- Instruction bus signals
signal idata : std_logic_vector(31 downto 0);
Expand All @@ -96,6 +94,7 @@ architecture rtl of de10_lite is

-- I/O signals
signal input_in : std_logic_vector(31 downto 0);
signal ddata_r_gpio : std_logic_vector(31 downto 0);

-- PLL signals
signal locked_sig : std_logic;
Expand All @@ -115,19 +114,8 @@ architecture rtl of de10_lite is
signal burst : std_logic;
signal byteenable : std_logic_vector(1 downto 0);

-- VGA signals
signal vga_addr : std_logic_vector(31 downto 0);
signal disp_ena : std_logic;
signal n_blank : std_logic;
signal n_sync : std_logic;
signal column : integer;
signal row : integer;
signal vga_data_read : std_logic;
signal buffer_to_sdram_addr : std_logic_vector(31 downto 0);
signal VGA_RR : std_logic_vector(3 downto 0);
signal VGA_GG : std_logic_vector(3 downto 0);
signal VGA_BB : std_logic_vector(3 downto 0);
signal chipselect_core : std_logic;
signal gpio_input : std_logic_vector(31 downto 0);
signal gpio_output : std_logic_vector(31 downto 0);

begin

Expand All @@ -137,13 +125,12 @@ begin
inclk0 => MAX10_CLK1_50,
c0 => clk,
c1 => clk_sdram_ctrl,
c2 => clk_vga,
c3 => clk_sdram_chip,
c2 => open,
c3 => open,
locked => locked_sig
);

rst <= SW(9);
rst_n <= SW(8);

-- Dummy out signals
ARDUINO_IO <= ddata_r(31 downto 16);
Expand Down Expand Up @@ -192,13 +179,18 @@ begin
-- Adress space mux ((check sections.ld) -> Data chip select:
-- 0x00000 -> Instruction memory
-- 0x20000 -> Data memory
-- 0x40000 -> Input/Output generic address space
-- 0x60000 -> SDRAM address space
with dcsel select ddata_r <=
idata when "00",
ddata_r_mem when "01",
input_in when "10",
sdram_read_32 when "11",(others => '0') when others;
-- 0x40000 -> Input/Output generic address space
-- ( ... ) -> ( ... )
datamux: entity work.databusmux
port map(
dcsel => dcsel,
idata => idata,
ddata_r_mem => ddata_r_mem,
ddata_r_gpio => ddata_r_gpio,
ddata_r_sdram=> sdram_read_32,
ddata_r => ddata_r
);


-- sdram output is 16 bits while data bus is 32 bits
sdram_read_32 <= x"0000" & sdram_read;
Expand All @@ -224,77 +216,20 @@ begin
state => state
);

-- Output register (Dummy LED blinky)
process(clk, rst)
begin
if rst = '1' then
LEDR(4 downto 0) <= (others => '0');
HEX0 <= (others => '1');
HEX1 <= (others => '1');
HEX2 <= (others => '1');
HEX3 <= (others => '1');
HEX4 <= (others => '1');
HEX5 <= (others => '1');
else
if rising_edge(clk) then
if (d_we = '1') and (dcsel = "10") then
-- ToDo: Simplify compartors
-- ToDo: Maybe use byte addressing?
-- x"01" (word addressing) is x"04" (byte addressing)
if to_unsigned(daddress, 32)(8 downto 0) = x"01" then
LEDR(4 downto 0) <= sdram_read(4 downto 0);
elsif to_unsigned(daddress, 32)(8 downto 0) = x"02" then
HEX0 <= sdram_read(7 downto 0);
HEX1 <= sdram_read(15 downto 8);
--HEX2 <= ddata_w(23 downto 16);
--HEX3 <= ddata_w(31 downto 24);
-- HEX4 <= ddata_w(7 downto 0);
-- HEX5 <= ddata_w(7 downto 0);
end if;
end if;
end if;
end if;
end process;

-- Input register
process(clk, rst)
begin
if rst = '1' then
input_in <= (others => '0');
else
if rising_edge(clk) then
if (d_we = '1') and (dcsel = "10") then
input_in(4 downto 0) <= SW(4 downto 0);
end if;
end if;
end if;
end process;

-- CORE, VGA and SDRAM muxes
with SW(7) select sdram_addr <=
daddress_to_sdram when '1',
buffer_to_sdram_addr when others;

with SW(7) select sdram_d_rd <=
d_rd when '1',
vga_data_read when others;

with SW(7) select chipselect_sdram <=
chipselect_core when '1',
vga_data_read when others;

with SW(7) select burst <=
'0' when '1',
'1' when others;
sdram_addr <= daddress_to_sdram;
sdram_d_rd <= d_rd;
burst <='0'; -- Todo Adicionar suporte a 32bits

-- SDRAM instatiation
sdram_controller : entity work.sdram_controller
port map(
address => sdram_addr,
byteenable => byteenable,
byteenable => dmask(1 downto 0),
chipselect => chipselect_sdram,
clk => clk_sdram_ctrl,
clken => byteenable(0),
clken => dmask(0),
reset => rst,
reset_req => rst,
write => d_we,
Expand All @@ -308,67 +243,53 @@ begin
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => open,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N
);

DRAM_CLK <= clk_sdram_chip;
-- SDRAM Signals
daddress_to_sdram <= std_logic_vector(to_unsigned(daddress, 32));
DRAM_UDQM <= DRAM_DQM(1);
DRAM_LDQM <= DRAM_DQM(0);
--chipselect_sdram <= dcsel(0) and dcsel(1);
chipselect_core <= dcsel(0) and dcsel(1);
byteenable <= SW(6 downto 5);

-- vga_controller : entity work.vga_controller
-- port map(
-- pixel_clk => clk_vga,
-- reset_n => rst_n,
-- h_sync => VGA_HS,
-- v_sync => VGA_VS,
-- disp_ena => disp_ena,
-- column => column,
-- row => row,
-- addr => vga_addr,
-- n_blank => n_blank,
-- n_sync => n_sync
-- );
--
-- vga_buffer : entity work.vga_buffer
-- port map(
-- clk => clk_sdram_ctrl,
-- rst => rst,
-- address_vga => vga_addr,
-- sdram_data => sdram_read,
-- sdram_address => buffer_to_sdram_addr,
-- sdram_r => vga_data_read,
-- VGA_R => VGA_RR,
-- VGA_G => VGA_GG,
-- VGA_B => VGA_BB
-- );


PROCESS(disp_ena)
BEGIN

IF(disp_ena = '1') THEN --display time
VGA_R <= VGA_RR;
VGA_G <= VGA_GG;
VGA_B <= VGA_BB;
ELSE --blanking time
VGA_R <= "0000";
VGA_G <= "0000";
VGA_B <= "0000";
END IF;

END PROCESS;

chipselect_sdram <= dcsel(0) and dcsel(1);
byteenable <= "11";

generic_gpio: entity work.gpio
generic map(
MY_CHIPSELECT => "10",
MY_WORD_ADDRESS => x"10"
)
port map(
clk => clk,
rst => rst,
daddress => daddress,
ddata_w => ddata_w,
ddata_r => ddata_r_gpio,
d_we => d_we,
d_rd => d_rd,
dcsel => dcsel,
dmask => dmask,
input => gpio_input,
output => gpio_output
);

-- Connect gpio data to output hardware
LEDR(7 downto 0) <= gpio_output(7 downto 0);
gpio_input(7 downto 0) <= SW(7 downto 0);
--LEDR(7 downto 0) <= sdram_read(7 downto 0);

-- Turn off all HEX displays
HEX0 <= (others => '1');
HEX1 <= (others => '1');
HEX2 <= (others => '1');
HEX3 <= (others => '1');
HEX4 <= (others => '1');
HEX5 <= (others => '1');

end;



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