implemented getPRID and a missing part of INITCPU

virtualsquare · Sep 28, 2024 · e6e4a3b · e6e4a3b
1 parent a49f906
commit e6e4a3b
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Showing 4 changed files with 53 additions and 10 deletions.
diff --git a/src/include/uriscv/csr.h b/src/include/uriscv/csr.h
@@ -51,5 +51,7 @@
 #define CSR_INDEX 0x802
 #define CSR_RANDOM 0x803
 #define CSR_BADVADDR 0x804
+#define PRID 0x805
+
 
 #endif
diff --git a/src/support/bios/exec.S b/src/support/bios/exec.S
@@ -30,7 +30,7 @@
 
 #define ASIDSTEP    0x00000040
 #define VPNMASK     0xFFFFF000
-#define VECTSIZE    140
+#define STATE_T_SIZE_IN_BYTES 148
 
 /* NOP padding: 30 nops - string length (32 bytes) */
 #define PANIC_PADDING    (30 * 4) - 32
@@ -72,7 +72,7 @@ bios:
 	 * 0x00000000 address
 	 * This is the entry point for UTLB type exceptions.
 	 */
-	j	LEXCHandler
+	j   LEXCHandler
 	nop
 
 EndStr:
@@ -86,6 +86,45 @@ PanicStr:
 	 * 0x00000080: panic()
 	 * Print a message on terminal 0 and loop forever
 	 */
+    j   LPanic
+    nop
+
+	.space	0x80 - 0x8
+     /*
+	 * 0x00000100 address
+	 * Secondary processor startup routine
+	 */
+    j   LInitSecondaryProcessor
+	nop
+
+/*
+ * Get a cpu up and runing: initialize BIOS related structures and
+ * load the supplied processor state.
+ */
+LInitSecondaryProcessor:
+	/* Initialize ptr to exception state vector */
+	li	t0, STATE_T_SIZE_IN_BYTES
+    csrrw t1, PRID, zero
+	mul	t0, t0, t1
+	li	t2, BIOS_DATA_PAGE_BASE
+	add	t0, t0, t2
+	li	t2, BIOS_EXCPT_VECT_BASE
+	sw	t0, 0(t2)
+
+	/* Initialize ptr to PC/SP area */
+	li	t0, 16
+	mul t0, t0, t1
+	li	t1, BIOS_EXEC_HANDLERS_ADDRS
+	add	t0, t0, t1
+	li	t2, BIOS_PC_AREA_BASE
+	sw	t0, 0(t2)
+
+	/* Load the new state - address of start_state cached at start of exception vector */
+	li	t0, BIOS_EXCPT_VECT_BASE
+	lw	t2, 0(t0)
+    lw  t2, 0(t2)
+    WRITEK0(t2)
+	j	LLoadStart
 
 LPanic:
 	li	a0, PANICSTRADDR - 1

diff --git a/src/support/liburiscv/liburiscv.S b/src/support/liburiscv/liburiscv.S
@@ -3,6 +3,9 @@
 #include "uriscv/cpu.h"
 #include "uriscv/const.h"
 
+#define STATE_T_SIZE_IN_BYTES 148 
+#define INIT_SECONDARY_PROCESSOR_ROUTINE_ADDRESS 0x00000100  
+
 #define LEAF_FUNC(func)				\
 	.globl	func;              \
 	.type	func, @function;   \
@@ -78,7 +81,7 @@ LEAF_FUNC(getEPC)
 	jr	ra
 
 LEAF_FUNC(getPRID)
-  addi a0,a0,3
+  csrrw a0,PRID,zero
 	jr	ra
 
 LEAF_FUNC(getMIE)
@@ -325,28 +328,25 @@ LEAF_FUNC(PANIC)
  */
 LEAF_FUNC(INITCPU)
 	li	t0, MCTL_BOOT_PC
-	li	t1, 0x00000100
+	li	t1, INIT_SECONDARY_PROCESSOR_ROUTINE_ADDRESS 
+
 	sw	t1, 0(t0)
 
 	/* Compute starting address for this CPUs stored exception vector */
-	li	t0, 140    /* 140 is the size of a state_t vector */
+	li	t0, STATE_T_SIZE_IN_BYTES 
 	mul t0, t0, a0
 	li	t1, BIOS_DATA_PAGE_BASE
 	add	t0, t1, t0
 
 	/* store start_state at start of this CPU's stored exception vector */
 	sw	a1, 0(t0)
 
-	/*.set	noreorder*/
 	li	t0, MCTL_RESET_CPU
 	sw	a0, 0(t0)
-	/*.set	reorder*/
 
 	jr	ra
 
-/*
- * CAS instruction wrapper
- */
+
 LEAF_FUNC(ACQUIRE_LOCK)
 	li a1, 0
 	li a2, 0

diff --git a/src/uriscv/processor.cc b/src/uriscv/processor.cc
@@ -169,6 +169,7 @@ void Processor::initCSR() {
 
   csr[TIME].perm = RRR;
   csr[TIMEH].perm = RRR;
+  csr[PRID].perm = RRR;
 
   csr[INSTRET].perm = RRR;
   csr[MINSTRET].perm = NNW;
@@ -283,6 +284,7 @@ void Processor::Reset(Word pc, Word sp) {
   csrWrite(MIE, 0);
   csrWrite(MCAUSE, 0);
   csrWrite(TIME, 0);
+  csrWrite(PRID, id);
   mode = 0x3;
 
   currPC = pc;