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6 changes: 6 additions & 0 deletions plugin/verilog_systemverilog.vim
Original file line number Diff line number Diff line change
Expand Up @@ -169,6 +169,12 @@ let g:verilog_syntax = {
\ 'highlight' : 'verilogStatement',
\ 'syn_argument': 'transparent keepend contains=ALLBUT,verilogInterface',
\ }],
\ 'ovm' : [{
\ 'match_start' : '`\<\(ovm\|uvm\)_\a\+_utils_begin\>',
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[ou]vm ? ;)

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In hindsight that does seem a little simpler ;)

\ 'match_end' : '`\<\(ovm\|uvm\)_\a\+_utils_end\>',
\ 'highlight' : 'verilogStatement',
\ 'syn_argument': 'transparent keepend',
\ }],
\ 'property' : [{
\ 'match_start' : '\<\(\(assert\|cover\)\s\+\)\@<!\<property\>',
\ 'match_end' : '\<endproperty\>',
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1 change: 1 addition & 0 deletions syntax/verilog_systemverilog.vim
Original file line number Diff line number Diff line change
Expand Up @@ -219,6 +219,7 @@ let s:verilog_syntax_order = [
\ 'function',
\ 'interface',
\ 'module',
\ 'ovm',
\ 'property',
\ 'sequence',
\ 'specify',
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