verilog-to-routing · AlexandreSinger · Jun 25, 2025 · Jun 19, 2025 · Jun 19, 2025 · Jun 20, 2025
diff --git a/.gitmodules b/.gitmodules
@@ -10,3 +10,6 @@
 [submodule "libs/EXTERNAL/libezgl"]
 	path = libs/EXTERNAL/libezgl
 	url = https://github.com/verilog-to-routing/ezgl.git
+[submodule "libs/EXTERNAL/yosys"]
+	path = libs/EXTERNAL/yosys
+	url = https://github.com/YosysHQ/yosys.git
diff --git a/CMakeLists.txt b/CMakeLists.txt
@@ -413,24 +413,6 @@ if(${WITH_ABC})
     add_subdirectory(abc)
 endif()
 
-if(${WITH_PARMYS}) # define cmake params to compile Yosys
-    add_definitions("-D_YOSYS_")
-
-    set(MAKE_PROGRAM "$(MAKE)")
-    if(${CMAKE_GENERATOR} STREQUAL "Ninja")
-        set(MAKE_PROGRAM "make")
-    endif()
-
-    # Commented out since a make file should not call another make command with
-    # threads. It should pass this information from the parent automatically.
-    # if(NOT DEFINED "${CMAKE_BUILD_PARALLEL_LEVEL}")
-    #     set(CUSTOM_BUILD_PARALLEL_LEVEL 16)
-    # else()
-    #     set(CUSTOM_BUILD_PARALLEL_LEVEL "${CMAKE_BUILD_PARALLEL_LEVEL}")
-    # endif()
-    add_subdirectory(yosys)
-endif()
-
 add_subdirectory(libs) #libs/CMakeLists.txt handles adding warnings flags to non-external libraries
 
 if(${WITH_PARMYS})

diff --git a/dev/subtree_config.xml b/dev/subtree_config.xml
@@ -49,11 +49,6 @@
         internal_path="vtr_flow/benchmarks/system_verilog/fx68k"
         external_url="https://github.com/ijor/fx68k.git"
         default_external_ref="master"/>
-    <subtree
-        name="yosys"
-        internal_path="yosys"
-        external_url="https://github.com/YosysHQ/yosys.git"
-        default_external_ref="yosys-0.32"/>
     <subtree
         name="parmys"
         internal_path="parmys"

diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt
@@ -38,6 +38,47 @@ endif ()
 # The VTR root CMakeFile initializes the WITH_PARMYS
 if (${WITH_PARMYS})
 
+	cmake_minimum_required(VERSION 3.16)
+
+	#project(yosys)
+
+	# Create a target out of the library compilation result
+	SET(YOSYS_SRC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys)
+	SET(YOSYS_BUILD_DIR ${CMAKE_BINARY_DIR}/bin/yosys)
+
+    add_definitions("-D_YOSYS_")
+    set(MAKE_PROGRAM "$(MAKE)")
+	set(CURRENT_CPPFLAGS "$(CPPFLAGS)-w")
+	if(${CMAKE_GENERATOR} STREQUAL "Ninja")
+	    set(CURRENT_CPPFLAGS "-w")
+	endif()
+
+	#Initialize yosys submodules
+	execute_process(
+	 COMMAND git submodule update --init
+	 WORKING_DIRECTORY ${YOSYS_SRC_DIR}
+	)
+	execute_process(
+	  COMMAND ${GIT_EXECUTABLE} submodule foreach --recursive git\ submodule\ update\ --init
+	  WORKING_DIRECTORY ${YOSYS_SRC_DIR}
+	)
+
+	# how to build the result of the library
+	add_custom_command(OUTPUT ${YOSYS_BUILD_DIR}
+		COMMAND ${MAKE_PROGRAM} -C ${YOSYS_SRC_DIR}
+		    ENABLE_ABC=0
+		    PREFIX=${CMAKE_BINARY_DIR}
+
+		 COMMAND ${MAKE_PROGRAM} 
+		    -C ${YOSYS_SRC_DIR}
+		    install
+		    ENABLE_ABC=0
+		    PREFIX=${CMAKE_BINARY_DIR}
+
+		WORKING_DIRECTORY ${YOSYS_SRC_DIR})
+
+	add_custom_target(yosys ALL DEPENDS ${YOSYS_BUILD_DIR})
+
     if (${SYNLIG_SYSTEMVERILOG})
 
         set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog)
@@ -175,4 +216,4 @@ if (VPR_USE_SERVER)
             $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/sockpp/include>
             $<INSTALL_INTERFACE:include>
             )
-endif()
+endif()
diff --git a/libs/EXTERNAL/yosys b/libs/EXTERNAL/yosys
diff --git a/parmys/CMakeLists.txt b/parmys/CMakeLists.txt
@@ -19,7 +19,7 @@ add_library(parmys SHARED
 )
 target_include_directories(parmys PUBLIC ${LIB_INCLUDE_DIRS})
 target_include_directories(parmys PUBLIC ${LIB_INCLUDE_DIRS_O})
-target_include_directories(parmys PUBLIC ${VTR_SOURCE_DIR}/yosys/share/include)
+target_include_directories(parmys PUBLIC ${VTR_SOURCE_DIR}/libs/EXTERNAL/yosys/share/include)
 
 add_definitions("-D_YOSYS_")
 add_dependencies(parmys yosys)

diff --git a/parmys/regression_test/benchmark/task/freecores/synthesis_result.json b/parmys/regression_test/benchmark/task/freecores/synthesis_result.json
@@ -483,7 +483,7 @@
         "Average Path": 3,
         "Estimated LUTs": 4777,
         "Total Node": 1957,
-        "Wires": 5594,
+        "Wires": 5592,
         "Wire Bits": 10106,
         "Public Wires": 240,
         "Public Wire Bits": 240,

diff --git a/parmys/regression_test/benchmark/task/keywords/and/synthesis_result.json b/parmys/regression_test/benchmark/task/keywords/and/synthesis_result.json
@@ -95,21 +95,21 @@
         "test_name": "and/replicate_and_int_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "and/replicate_and_ultra_wide/no_arch": {
         "test_name": "and/replicate_and_ultra_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "and/replicate_and_wide/no_arch": {
         "test_name": "and/replicate_and_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "DEFAULT": {

diff --git a/parmys/regression_test/benchmark/task/keywords/nand/synthesis_result.json b/parmys/regression_test/benchmark/task/keywords/nand/synthesis_result.json
@@ -94,21 +94,21 @@
         "test_name": "nand/replicate_nand_int_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "nand/replicate_nand_ultra_wide/no_arch": {
         "test_name": "nand/replicate_nand_ultra_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "nand/replicate_nand_wide/no_arch": {
         "test_name": "nand/replicate_nand_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "DEFAULT": {

diff --git a/parmys/regression_test/benchmark/task/keywords/nor/synthesis_result.json b/parmys/regression_test/benchmark/task/keywords/nor/synthesis_result.json
@@ -100,21 +100,21 @@
         "test_name": "nor/replicate_nor_int_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "nor/replicate_nor_ultra_wide/no_arch": {
         "test_name": "nor/replicate_nor_ultra_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "nor/replicate_nor_wide/no_arch": {
         "test_name": "nor/replicate_nor_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "DEFAULT": {

diff --git a/parmys/regression_test/benchmark/task/keywords/or/synthesis_result.json b/parmys/regression_test/benchmark/task/keywords/or/synthesis_result.json
@@ -95,21 +95,21 @@
         "test_name": "or/replicate_or_int_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "or/replicate_or_ultra_wide/no_arch": {
         "test_name": "or/replicate_or_ultra_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "or/replicate_or_wide/no_arch": {
         "test_name": "or/replicate_or_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "DEFAULT": {

diff --git a/parmys/regression_test/benchmark/task/keywords/xnor/synthesis_result.json b/parmys/regression_test/benchmark/task/keywords/xnor/synthesis_result.json
@@ -54,21 +54,21 @@
         "test_name": "xnor/replicate_xnor_int_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "xnor/replicate_xnor_ultra_wide/no_arch": {
         "test_name": "xnor/replicate_xnor_ultra_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "xnor/replicate_xnor_wide/no_arch": {
         "test_name": "xnor/replicate_xnor_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "xnor/xnor_indexed_port/no_arch": {

diff --git a/parmys/regression_test/benchmark/task/keywords/xor/synthesis_result.json b/parmys/regression_test/benchmark/task/keywords/xor/synthesis_result.json
@@ -51,21 +51,21 @@
         "test_name": "xor/replicate_xor_int_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "xor/replicate_xor_ultra_wide/no_arch": {
         "test_name": "xor/replicate_xor_ultra_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "xor/replicate_xor_wide/no_arch": {
         "test_name": "xor/replicate_xor_wide/no_arch",
         "exit": 1,
         "errors": [
-            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
+            "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
         ]
     },
     "xor/xor_indexed_port/no_arch": {

diff --git a/parmys/regression_test/benchmark/task/koios/koios_medium_no_hb/synthesis_result.json b/parmys/regression_test/benchmark/task/koios/koios_medium_no_hb/synthesis_result.json
@@ -464,7 +464,7 @@
         "Estimated LUTs": 22752,
         "Total Node": 5094,
         "Wires": 24045,
-        "Wire Bits": 37311,
+        "Wire Bits": 37590,
         "Public Wires": 5228,
         "Public Wire Bits": 5228,
         "Total Cells": 24019,

diff --git a/parmys/regression_test/benchmark/task/syntax/synthesis_result.json b/parmys/regression_test/benchmark/task/syntax/synthesis_result.json
@@ -2924,8 +2924,8 @@
         "Average Path": 4,
         "Estimated LUTs": 101,
         "Total Node": 67,
-        "Wires": 213,
-        "Wire Bits": 269,
+        "Wires": 212,
+        "Wire Bits": 268,
         "Public Wires": 177,
         "Public Wire Bits": 177,
         "Total Cells": 145,
@@ -2964,8 +2964,8 @@
         "Average Path": 5,
         "Estimated LUTs": 25938,
         "Total Node": 34130,
-        "Wires": 76078,
-        "Wire Bits": 84564,
+        "Wires": 76077,
+        "Wire Bits": 84563,
         "Public Wires": 75169,
         "Public Wire Bits": 75169,
         "Total Cells": 59068,
@@ -4048,8 +4048,8 @@
         "Average Path": 4,
         "Estimated LUTs": 101,
         "Total Node": 33,
-        "Wires": 104,
-        "Wire Bits": 169,
+        "Wires": 103,
+        "Wire Bits": 168,
         "Public Wires": 71,
         "Public Wire Bits": 71,
         "Total Cells": 111,
@@ -4086,8 +4086,8 @@
         "Average Path": 4,
         "Estimated LUTs": 33,
         "Total Node": 33,
-        "Wires": 104,
-        "Wire Bits": 169,
+        "Wires": 103,
+        "Wire Bits": 168,
         "Public Wires": 71,
         "Public Wire Bits": 71,
         "Total Cells": 111,

diff --git a/parmys/regression_test/benchmark/task/ultraembedded/synthesis_result.json b/parmys/regression_test/benchmark/task/ultraembedded/synthesis_result.json
@@ -318,7 +318,7 @@
         "Average Path": 2,
         "Estimated LUTs": 2852,
         "Total Node": 1381,
-        "Wires": 3620,
+        "Wires": 3619,
         "Wire Bits": 5288,
         "Public Wires": 119,
         "Public Wire Bits": 119,

diff --git a/parmys/regression_test/benchmark/task/vexriscv/synthesis_result.json b/parmys/regression_test/benchmark/task/vexriscv/synthesis_result.json
@@ -412,14 +412,14 @@
         "Average Path": 4,
         "Estimated LUTs": 8043,
         "Total Node": 4065,
-        "Wires": 14723,
-        "Wire Bits": 20361,
+        "Wires": 14711,
+        "Wire Bits": 20350,
         "Public Wires": 877,
         "Public Wire Bits": 877,
-        "Total Cells": 17350,
+        "Total Cells": 17352,
         "MUX": 6882,
         "XOR": 454,
-        "OR": 2548,
+        "OR": 2550,
         "AND": 1968,
         "NOT": 926,
         "DFFs": [
@@ -1068,8 +1068,8 @@
         "Average Path": 4,
         "Estimated LUTs": 3240,
         "Total Node": 1609,
-        "Wires": 5551,
-        "Wire Bits": 8226,
+        "Wires": 5545,
+        "Wire Bits": 8284,
         "Public Wires": 421,
         "Public Wire Bits": 421,
         "Total Cells": 6825,
@@ -1231,8 +1231,8 @@
         "Average Path": 3,
         "Estimated LUTs": 3582,
         "Total Node": 1645,
-        "Wires": 5932,
-        "Wire Bits": 8679,
+        "Wires": 5926,
+        "Wire Bits": 8737,
         "Public Wires": 464,
         "Public Wire Bits": 464,
         "Total Cells": 7324,
@@ -1591,8 +1591,8 @@
         "Average Path": 4,
         "Estimated LUTs": 4666,
         "Total Node": 1960,
-        "Wires": 8365,
-        "Wire Bits": 11515,
+        "Wires": 8363,
+        "Wire Bits": 11514,
         "Public Wires": 584,
         "Public Wire Bits": 584,
         "Total Cells": 9682,
@@ -1653,8 +1653,8 @@
         "Average Path": 5,
         "Estimated LUTs": 3806,
         "Total Node": 1594,
-        "Wires": 7020,
-        "Wire Bits": 9597,
+        "Wires": 7019,
+        "Wire Bits": 9660,
         "Public Wires": 580,
         "Public Wire Bits": 580,
         "Total Cells": 7824,
@@ -1716,7 +1716,7 @@
         "Estimated LUTs": 3906,
         "Total Node": 1703,
         "Wires": 7427,
-        "Wire Bits": 10005,
+        "Wire Bits": 10069,
         "Public Wires": 694,
         "Public Wire Bits": 694,
         "Total Cells": 8164,
@@ -1759,8 +1759,8 @@
         "Average Path": 5,
         "Estimated LUTs": 3318,
         "Total Node": 1264,
-        "Wires": 5960,
-        "Wire Bits": 8305,
+        "Wires": 5959,
+        "Wire Bits": 8368,
         "Public Wires": 361,
         "Public Wire Bits": 361,
         "Total Cells": 6640,
@@ -1819,7 +1819,7 @@
         "Estimated LUTs": 6611,
         "Total Node": 2574,
         "Wires": 10970,
-        "Wire Bits": 15142,
+        "Wire Bits": 15143,
         "Public Wires": 583,
         "Public Wire Bits": 583,
         "Total Cells": 13096,
@@ -1865,7 +1865,7 @@
         "Average Path": 3,
         "Estimated LUTs": 7117,
         "Total Node": 3035,
-        "Wires": 12002,
+        "Wires": 12001,
         "Wire Bits": 16343,
         "Public Wires": 699,
         "Public Wire Bits": 699,
@@ -2160,7 +2160,7 @@
         "Estimated LUTs": 3513,
         "Total Node": 1415,
         "Wires": 6614,
-        "Wire Bits": 8797,
+        "Wire Bits": 8861,
         "Public Wires": 478,
         "Public Wire Bits": 478,
         "Total Cells": 7100,
@@ -2220,8 +2220,8 @@
         "Average Path": 4,
         "Estimated LUTs": 8969,
         "Total Node": 2639,
-        "Wires": 13230,
-        "Wire Bits": 18722,
+        "Wires": 13228,
+        "Wire Bits": 18784,
         "Public Wires": 674,
         "Public Wire Bits": 674,
         "Total Cells": 16338,
@@ -2269,7 +2269,7 @@
         "Estimated LUTs": 2048,
         "Total Node": 748,
         "Wires": 3124,
-        "Wire Bits": 4601,
+        "Wire Bits": 4665,
         "Public Wires": 349,
         "Public Wire Bits": 349,
         "Total Cells": 3750,
@@ -2315,7 +2315,7 @@
         "Estimated LUTs": 2023,
         "Total Node": 693,
         "Wires": 2983,
-        "Wire Bits": 4427,
+        "Wire Bits": 4491,
         "Public Wires": 253,
         "Public Wire Bits": 253,
         "Total Cells": 3623,
@@ -2361,7 +2361,7 @@
         "Estimated LUTs": 1535,
         "Total Node": 673,
         "Wires": 2398,
-        "Wire Bits": 3869,
+        "Wire Bits": 3933,
         "Public Wires": 253,
         "Public Wire Bits": 253,
         "Total Cells": 3009,
@@ -2407,7 +2407,7 @@
         "Estimated LUTs": 1190,
         "Total Node": 537,
         "Wires": 1958,
-        "Wire Bits": 3396,
+        "Wire Bits": 3460,
         "Public Wires": 250,
         "Public Wire Bits": 250,
         "Total Cells": 2564,

diff --git a/yosys/.clang-format b/yosys/.clang-format
diff --git a/yosys/.dockerignore b/yosys/.dockerignore
diff --git a/yosys/.editorconfig b/yosys/.editorconfig
diff --git a/yosys/.gitattributes b/yosys/.gitattributes
diff --git a/yosys/.gitcommit b/yosys/.gitcommit
diff --git a/yosys/.github/ISSUE_TEMPLATE/bug_report.yml b/yosys/.github/ISSUE_TEMPLATE/bug_report.yml
diff --git a/yosys/.github/ISSUE_TEMPLATE/config.yml b/yosys/.github/ISSUE_TEMPLATE/config.yml
diff --git a/yosys/.github/ISSUE_TEMPLATE/docs_report.yml b/yosys/.github/ISSUE_TEMPLATE/docs_report.yml
diff --git a/yosys/.github/ISSUE_TEMPLATE/feature_request.yml b/yosys/.github/ISSUE_TEMPLATE/feature_request.yml
diff --git a/yosys/.github/PULL_REQUEST_TEMPLATE.md b/yosys/.github/PULL_REQUEST_TEMPLATE.md
diff --git a/yosys/.github/actions/setup-build-env/action.yml b/yosys/.github/actions/setup-build-env/action.yml
diff --git a/yosys/.github/workflows/codeql.yml b/yosys/.github/workflows/codeql.yml
diff --git a/yosys/.github/workflows/extra-builds.yml b/yosys/.github/workflows/extra-builds.yml
diff --git a/yosys/.github/workflows/prepare-docs.yml b/yosys/.github/workflows/prepare-docs.yml
diff --git a/yosys/.github/workflows/source-vendor.yml b/yosys/.github/workflows/source-vendor.yml
diff --git a/yosys/.github/workflows/test-build.yml b/yosys/.github/workflows/test-build.yml
diff --git a/yosys/.github/workflows/test-compile.yml b/yosys/.github/workflows/test-compile.yml
diff --git a/yosys/.github/workflows/test-verific.yml b/yosys/.github/workflows/test-verific.yml
diff --git a/yosys/.github/workflows/update-flake-lock.yml b/yosys/.github/workflows/update-flake-lock.yml
diff --git a/yosys/.github/workflows/version.yml b/yosys/.github/workflows/version.yml
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