Generalize Parmys Mult_Split to Allow for Multipliers Whose Input Widths are not Equal #3143
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WhiteNinjaZ
changed the title
AmirhosseinPoolad
requested changes
Jun 17, 2025
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Thanks for the PR @WhiteNinjaZ, great fix! I didn't review your code changes in Parmys (Leaving that for someone more experienced in that part of the codebase) but since you added a new circuit to vtr_nightly_test2/vtr_xilinx_qor you should generate golden results for it because it would fail the NightlyTestManual CI test otherwise.
Keep in mind that I'm changing the way the results for this test is being parsed in #3138 so make sure you rebase/merge your changes after that PR is merged and generate golden results on top of the new master.
vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/config.txt
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Description
This PR fixes issue #2532. Several benchmarks including difeq2.v and mcml.v where failing parmys on the 7-series due to the 7-series DSP blocks having unequal input widths (25x18). This was caused due to parmys assuming that input widths where always equal in its multiplier splitter. This PR removes that assumption and allows for both types of multipliers to be split properly.
How Has This Been Tested?
Several Verilog designs with a variety of multiplier sizes where synthesized onto a modified version of the k6_frac_N10 arch that included multipliers of various sizes and different input widths (i.e. 18x25). The 7series_BRAM_DSP_carry.xml arch was also used for testing.
Types of changes
Checklist: