Add Xilinx arch tests to CI

dev/vtr_test_suite_verifier/test_suites_info.json

@@ -19,14 +19,12 @@
         "name": "vtr_reg_strong",
         "ignored_tasks": [
             "strong_router_heap",
-            "strong_verify_rr_graph_3d",
-            "strong_xilinx_support"
+            "strong_verify_rr_graph_3d"
         ]
     },
     {
         "name": "vtr_reg_strong_odin",
         "ignored_tasks": [
-            "strong_xilinx_support",
             "strong_router_heap",
             "strong_cluster_seed_type"
         ]
@@ -44,8 +42,7 @@
         "name": "vtr_reg_nightly_test2",
         "ignored_tasks": [
             "complex_switch",
-            "vpr_verify_custom_sb_diff_chan_width",
-            "vtr_xilinx_qor"
+            "vpr_verify_custom_sb_diff_chan_width"
         ]
     },
     {

vtr_flow/arch/xilinx/7series_BRAM_DSP_carry.xml

@@ -956,7 +956,8 @@
             <interconnect>
               <mux name="cin" input="fle.cin fle.inX" output="adder.cin">
                 <pack_pattern name="chain" in_port="fle.cin" out_port="adder.cin" />
-                <pack_pattern name="chain2" in_port="fle.inX" out_port="adder.cin" />
+                <!-- <pack_pattern name="chain" in_port="fle.inX" out_port="adder.cin" /> -->
+                <!-- Not currently supported but more accurate. Commented out for now. -->
               </mux>
               <direct name="cout" input="adder.cout" output="fle.cout">
                 <pack_pattern name="chain" in_port="adder.cout" out_port="fle.cout" />
@@ -981,7 +982,6 @@
               <!-- mux for the input to the inner FF of each SLICE_L -->
               <mux name="FFMUX" input="ALUT.O5 fle.inX" output="FDSE[0].D">
                 <pack_pattern name="ff_in" in_port="ALUT.O5" out_port="FDSE[0].D" />
-                <pack_pattern name="ff_in2" in_port="fle.inX" out_port="FDSE[0].D" />
                 <delay_constant in_port="fle.inX" max="2.0200000000000003e-10"
                   out_port="FDSE[0].D" />
                 <delay_constant in_port="ALUT.O5" max="1.07e-10"

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt

@@ -11,3 +11,4 @@ regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan
 regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc
 regression_tests/vtr_reg_nightly_test2/titan_other
 regression_tests/vtr_reg_nightly_test2/titan_quick_qor
+regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/config.txt

@@ -0,0 +1,20 @@
+circuits_dir=benchmarks/verilog
+
+archs_dir=arch/xilinx
+
+arch_list_add=7series_BRAM_DSP_carry.xml
+
+# Add circuits to list to sweep
+circuit_list_add=stereovision3.v
+
+
+# Parse info and how to parse
+parse_file=vpr_standard.txt
+
+# How to parse QoR info
+qor_parse_file=qor_standard.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements.txt
+
+script_params=-track_memory_usage

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/golden_results.txt

@@ -0,0 +1,2 @@
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
+7series_BRAM_DSP_carry.xml	stereovision3.v	common	2.87	vpr	72.69 MiB		-1	-1	0.32	26404	4	0.08	-1	-1	35804	-1	-1	-1	11	0	-1	success	v8.0.0-12999-gf153e4447-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-5.15.0-119-generic x86_64	2025-06-12T17:00:21	goeders10	/home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks	74436	11	2	303	283	2	114	35	7	7	49	CLB	auto	33.4 MiB	1.15	577.007	408	947	108	584	255	72.7 MiB	0.01	0.00	3.1717	3.1717	-180.982	-3.1717	2.89952	0.12	0.000180919	0.000138049	0.00514751	0.00458797	-1	-1	-1	-1	40	911	27	1.34735e+06	1.18567e+06	152291.	3107.98	0.59	0.032835	0.0284564	6668	73471	-1	385	12	297	988	127228	60728	2.91111	2.8252	-221.503	-2.91111	-2.452	-0.04	215465.	4397.25	0.02	0.02	0.04	-1	-1	0.02	0.0099349	0.00925009	

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_support/config/config.txt → vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_simple/config/config.txt

@@ -1,5 +1,12 @@
+circuits_dir=benchmarks/verilog
+
+archs_dir=arch/xilinx
+
 arch_list_add=simple-7series.xml
 
+# Add circuits to list to sweep
+circuit_list_add=stereovision3.v
+
 
 # Parse info and how to parse
 parse_file=vpr_standard.txt

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_simple/config/golden_results.txt

@@ -0,0 +1,2 @@
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
+simple-7series.xml	stereovision3.v	common	2.34	vpr	61.75 MiB		-1	-1	0.33	26756	5	0.09	-1	-1	36584	-1	-1	14	10	0	-1	success	v8.0.0-12959-g807e5b42b	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-5.15.0-119-generic x86_64	2025-06-12T13:14:59	goeders10	/home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks	63232	10	2	181	183	1	68	26	7	7	49	clb	auto	22.5 MiB	0.56	361.432	259	634	104	490	40	61.8 MiB	0.01	0.00	2.44221	2.32405	-96.2707	-2.32405	2.32405	0.03	7.5285e-05	5.8418e-05	0.00218157	0.00190291	-1	-1	-1	-1	154	1672	14	0	0	294086.	6001.75	0.85	0.0161528	0.0139739	12242	48540	-1	1452	8	249	850	459780	251535	4.66751	4.66751	-159.78	-4.66751	-2.328	-0.04	377773.	7709.66	0.02	0.05	0.03	-1	-1	0.02	0.00426335	0.00401122	

vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt

@@ -105,3 +105,5 @@ regression_tests/vtr_reg_strong/strong_flat_router
 regression_tests/vtr_reg_strong/strong_routing_constraints
 regression_tests/vtr_reg_strong/strong_3d/3d_cb
 regression_tests/vtr_reg_strong/strong_3d/3d_sb
+regression_tests/vtr_reg_strong/strong_xilinx_simple
+regression_tests/vtr_reg_strong/strong_xilinx_flagship