Skip to content

[WIP] Tileable Routing Resource Graph Builder #2135

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 549 commits into
base: master
Choose a base branch
from
Open
Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
549 commits
Select commit Hold shift + click to select a range
91e62d5
[vpr] bypass 0-fan-in node in power estimator
tangxifan Jun 4, 2024
d1b89e5
Merge branch 'master' into openfpga
tangxifan Jun 4, 2024
82a1860
Merge branch 'master' into openfpga
tangxifan Jun 5, 2024
d8cd3db
resolve merge conflicts.
Tulong4Dev Jun 6, 2024
755662b
Merge pull request #2591 from verilog-to-routing/resolve_merge_conflict
tangxifan Jun 6, 2024
8ffc583
Merge branch 'master' into openfpga
tangxifan Jun 6, 2024
6e8ac62
Merge branch 'master' into openfpga
tangxifan Jun 9, 2024
7bd0433
Update physical_types.h
Wang-Yuanqi-source Jun 9, 2024
a0ecbce
Update read_xml_arch_file.cpp
Wang-Yuanqi-source Jun 9, 2024
16ab238
Update SetupGrid.cpp
Wang-Yuanqi-source Jun 9, 2024
35cccdc
Update vpr_context.h
Wang-Yuanqi-source Jun 9, 2024
7af8feb
Update SetupGrid.h
Wang-Yuanqi-source Jun 9, 2024
56a7e68
Update vpr_api.cpp
Wang-Yuanqi-source Jun 9, 2024
98e7992
Update tileable_rr_graph_edge_builder.cpp
Wang-Yuanqi-source Jun 9, 2024
5b32f84
Update tileable_rr_graph_builder.cpp
Wang-Yuanqi-source Jun 9, 2024
87d4b59
Update tileable_rr_graph_edge_builder.h
Wang-Yuanqi-source Jun 9, 2024
c23795c
Update tileable_rr_graph_node_builder.cpp
Wang-Yuanqi-source Jun 9, 2024
873469f
Update tileable_rr_graph_node_builder.h
Wang-Yuanqi-source Jun 9, 2024
307fb0b
Update read_xml_arch_file.cpp
Wang-Yuanqi-source Jun 15, 2024
77dfbe9
Update tileable_rr_graph_builder.cpp
Wang-Yuanqi-source Jun 15, 2024
55c4835
Update check_rr_graph.cpp
Wang-Yuanqi-source Jun 15, 2024
82151d4
Update check_route.cpp
Wang-Yuanqi-source Jun 15, 2024
fffdc02
Update rr_graph_uxsdcxx_serializer.h
Wang-Yuanqi-source Jun 15, 2024
71c60e2
Update rr_graph_uxsdcxx_interface.h
Wang-Yuanqi-source Jun 15, 2024
14eedda
Update rr_graph.cpp
Wang-Yuanqi-source Jun 15, 2024
ac8c197
Update rr_graph2.cpp
Wang-Yuanqi-source Jun 15, 2024
ed15d8a
Update vpr_utils.cpp
Wang-Yuanqi-source Jun 15, 2024
e508528
Update connection_router.cpp
Wang-Yuanqi-source Jun 15, 2024
08268fe
Update overuse_report.cpp
Wang-Yuanqi-source Jun 15, 2024
6abd0b7
Update vpr_utils.h
Wang-Yuanqi-source Jun 15, 2024
f80e4c3
Update router_lookahead_map_utils.cpp
Wang-Yuanqi-source Jun 15, 2024
92fd5af
Update router_lookahead_map.cpp
Wang-Yuanqi-source Jun 15, 2024
faf2ef3
Update rr_graph_uxsdcxx.h
Wang-Yuanqi-source Jun 15, 2024
601718a
Update rr_spatial_lookup.cpp
Wang-Yuanqi-source Jun 15, 2024
0541865
Update check_rr_graph.h
Wang-Yuanqi-source Jun 15, 2024
a2777e6
Update tileable_rr_graph_edge_builder.cpp
Wang-Yuanqi-source Jun 15, 2024
58dce81
Update tileable_rr_graph_gsb.cpp
Wang-Yuanqi-source Jun 15, 2024
5bb56c7
Update tileable_rr_graph_gsb.h
Wang-Yuanqi-source Jun 15, 2024
0929cd0
Update rr_node_types.h
Wang-Yuanqi-source Jun 15, 2024
6121423
Update rr_graph_builder.h
Wang-Yuanqi-source Jun 15, 2024
1d0be82
Update rr_graph_storage.cpp
Wang-Yuanqi-source Jun 15, 2024
e904c86
Update rr_graph_storage.h
Wang-Yuanqi-source Jun 15, 2024
25b096d
Update rr_graph_cost.h
Wang-Yuanqi-source Jun 15, 2024
e099206
Merge branch 'master' into openfpga
tangxifan Jun 18, 2024
fed10de
Merge branch 'master' into openfpga
tangxifan Jun 18, 2024
2ff460a
Merge branch 'master' into openfpga
tangxifan Jun 19, 2024
6a4f0ca
Merge branch 'master' into openfpga
tangxifan Jun 24, 2024
115d237
Removing warnings from libencrypt and libdecrypt
behzadmehmood Jun 25, 2024
03556c6
Merge branch 'openfpga' into patch-1
Wang-Yuanqi-source Jul 2, 2024
a7b8546
Merge branch 'master' of github.com:verilog-to-routing/vtr-verilog-to…
tangxifan Jul 3, 2024
e4ddd25
[vpr] add a new option to enable perimeter cbx and cby
tangxifan Jul 3, 2024
691ae6d
[vpr] updating tileable rr graph generator
tangxifan Jul 3, 2024
619e94e
[vpr] upgraded tileable rr_graph to support perimeter cb
tangxifan Jul 3, 2024
e4e158d
[vpr] syntax
tangxifan Jul 3, 2024
57dc489
[test] add perimeter_cb to strong test
tangxifan Jul 3, 2024
46dd4bf
[test] add new test
tangxifan Jul 3, 2024
c1f3c80
[vpr] fixed a bug on access invalid grid nodes
tangxifan Jul 3, 2024
76d69fb
[lib] relax check_rr_node on (x, y) range as now CHANX and CHANY can …
tangxifan Jul 3, 2024
3095c28
Merge branch 'master' into openfpga
tangxifan Jul 3, 2024
64bbd24
[vpr] typo on debug string
tangxifan Jul 4, 2024
7aa2304
[vpr] fix minor bug where sort edge is not applicable to boundary gsb…
tangxifan Jul 4, 2024
97c106c
[vpr] fixing a bug where sorted edges are not located
tangxifan Jul 4, 2024
b172d26
[vpr] now when cb on perimeter, I/O pins can access three sides
tangxifan Jul 4, 2024
ae9eb2d
[vpr] syntax
tangxifan Jul 4, 2024
b9bc0cb
[vpr] syntax
tangxifan Jul 4, 2024
159bea4
[vpr] syntax
tangxifan Jul 4, 2024
fbbf53d
[vpr] fixed a bug where perimeter cb are not connected to adjancet sbs
tangxifan Jul 4, 2024
19fa43c
[vpr] fixing some bugs in rr gsb
tangxifan Jul 4, 2024
589b6bc
[core] debug
tangxifan Jul 4, 2024
e9d5647
[vpr] now change to a simpler rr gsb coordinate system: grid is moved…
tangxifan Jul 5, 2024
d338952
[vpr] update gsb builder in tileable rr graph for changing the coordi…
tangxifan Jul 5, 2024
ba0576d
[vpr] syntax
tangxifan Jul 5, 2024
826a10b
[vpr] debugging
tangxifan Jul 5, 2024
b06f2ee
[core] fixed a bug where gsb nodes are not correctly added
tangxifan Jul 5, 2024
de0d0bc
[core] debug
tangxifan Jul 5, 2024
0a1bc20
[core] debugging
tangxifan Jul 5, 2024
4da28ff
[core] debug
tangxifan Jul 5, 2024
c71c3b9
[core] debug
tangxifan Jul 5, 2024
d2be1c8
[core] fixed a critical bug
tangxifan Jul 5, 2024
3eca1f6
Updating libencryption/libdecryption for compatibility with openssl3
behzadmehmood Jul 8, 2024
abf1ce6
Not dumping decrypted xml
behzadmehmood Jul 8, 2024
2f82dd7
Commenting unused variables in pugixml_loc.cpp
behzadmehmood Jul 8, 2024
11e3b5a
Merge branch 'openfpga' of https://github.com/verilog-to-routing/vtr-…
behzadmehmood Jul 8, 2024
2040d43
[core] fixed a bug where sb may go out of boundary
tangxifan Jul 8, 2024
5ca82e5
[core] code format
tangxifan Jul 8, 2024
ddc3ac4
[core] debugging
tangxifan Jul 8, 2024
67fe7a3
Minor changes for code clean-up
behzadmehmood Jul 9, 2024
e8b2ac7
Updating code to avoid possible memory leaks
behzadmehmood Jul 9, 2024
2482506
Dynamically allocating memory for session key
behzadmehmood Jul 9, 2024
7f1df67
Adding test for XML encryption/decryption
behzadmehmood Jul 10, 2024
18be453
Updating CMake for libencrypt
behzadmehmood Jul 10, 2024
6537c73
Correcting typo and removing valgrind call from workflow file
behzadmehmood Jul 10, 2024
dd5e470
Updating build path for Test_Encryption_Decryption
behzadmehmood Jul 10, 2024
75e8676
Update alloc_and_load_rr_indexed_data.cpp
Wang-Yuanqi-source Jul 13, 2024
0f81e94
Update read_route.cpp
Wang-Yuanqi-source Jul 13, 2024
9e0ae28
Update describe_rr_node.cpp
Wang-Yuanqi-source Jul 13, 2024
b65a8e2
Update check_route.cpp
Wang-Yuanqi-source Jul 13, 2024
abaec29
Update rr_graph_area.cpp
Wang-Yuanqi-source Jul 13, 2024
e6b7e7d
Update tileable_rr_graph_edge_builder.cpp
Wang-Yuanqi-source Jul 13, 2024
30dae5a
Update tileable_chan_details_builder.cpp
Wang-Yuanqi-source Jul 13, 2024
6d1dd98
added unit test for libdecryption
NadeemYaseen Jul 13, 2024
cc8816a
Update read_xml_arch_file.cpp
Wang-Yuanqi-source Jul 14, 2024
70e4f5a
Update vpr_utils.h
Wang-Yuanqi-source Jul 14, 2024
cabf2ea
Update vpr_utils.cpp
Wang-Yuanqi-source Jul 14, 2024
0ead1a8
Update router_lookahead_map_utils.cpp
Wang-Yuanqi-source Jul 14, 2024
07627be
Update tileable_rr_graph_builder.cpp
Wang-Yuanqi-source Jul 14, 2024
efb99fc
Update vpr_utils.cpp
Wang-Yuanqi-source Jul 14, 2024
510f4e2
Update SetupGrid.h
Wang-Yuanqi-source Jul 14, 2024
993aca5
Update SetupGrid.h
Wang-Yuanqi-source Jul 14, 2024
deb8802
Merge remote-tracking branch 'origin/openfpga' into rem_warnings
behzadmehmood Jul 15, 2024
9eef18c
Merge pull request #2629 from verilog-to-routing/rem_warnings
tangxifan Jul 30, 2024
68e4d65
Merge branch 'openfpga' into patch-1
Wang-Yuanqi-source Jul 30, 2024
51bd666
Merge branch 'master' into openfpga
tangxifan Jul 30, 2024
42829ed
Merge branch 'master' into openfpga
tangxifan Jul 31, 2024
af8895e
Merge branch 'master' into openfpga
tangxifan Aug 8, 2024
9dc2a45
Merge branch 'master' into openfpga
tangxifan Aug 28, 2024
83f8bfe
Merge branch 'master' into openfpga
tangxifan Oct 7, 2024
9ddf4ca
[core] adapt to side var changes
tangxifan Oct 7, 2024
585bd4f
[core] fixed a bug where sink node cannot be mirror
tangxifan Oct 7, 2024
727ecf6
Merge branch 'master' into openfpga
tangxifan Oct 7, 2024
2eb6eb6
Merge branch 'master' into openfpga
tangxifan Oct 8, 2024
7569f73
Merge branch 'master' into openfpga
tangxifan Oct 8, 2024
e677079
Merge branch 'master' into openfpga
tangxifan Oct 10, 2024
a3b55ea
Merge branch 'master' into openfpga
tangxifan Oct 17, 2024
876311a
[core] fix the bug where skip sync-routing results are not applicable…
tangxifan Oct 17, 2024
1afa2f5
Create vib_inf.cpp
Wang-Yuanqi-source Oct 22, 2024
f3deaa6
Create vib_inf.h
Wang-Yuanqi-source Oct 22, 2024
ccb5b56
Update rr_graph_storage.h
Wang-Yuanqi-source Oct 22, 2024
3769b62
Update physical_types.h
Wang-Yuanqi-source Oct 22, 2024
9e521a0
Update read_xml_arch_file.cpp
Wang-Yuanqi-source Oct 22, 2024
cb22a8a
Update check_rr_graph.cpp
Wang-Yuanqi-source Oct 22, 2024
487ed26
Update check_rr_graph.h
Wang-Yuanqi-source Oct 22, 2024
6382aaf
Update rr_graph_uxsdcxx_serializer.h
Wang-Yuanqi-source Oct 22, 2024
bb2d5cf
Update SetupGrid.cpp
Wang-Yuanqi-source Oct 22, 2024
b3bb7c8
Update SetupGrid.h
Wang-Yuanqi-source Oct 22, 2024
5b27ab8
Update vpr_api.cpp
Wang-Yuanqi-source Oct 22, 2024
345a27c
Update vpr_context.h
Wang-Yuanqi-source Oct 22, 2024
eeb448a
Update connection_router.cpp
Wang-Yuanqi-source Oct 22, 2024
0d7cacd
Update overuse_report.cpp
Wang-Yuanqi-source Oct 22, 2024
6f773cd
Update router_lookahead_map_utils.cpp
Wang-Yuanqi-source Oct 22, 2024
f7427aa
Update router_lookahead_map.cpp
Wang-Yuanqi-source Oct 22, 2024
d91bd9f
Update rr_graph.cpp
Wang-Yuanqi-source Oct 22, 2024
ce412a4
Update tileable_rr_graph_builder.cpp
Wang-Yuanqi-source Oct 22, 2024
d0f19a0
Update tileable_rr_graph_edge_builder.cpp
Wang-Yuanqi-source Oct 22, 2024
f117218
Update tileable_rr_graph_edge_builder.h
Wang-Yuanqi-source Oct 22, 2024
0e0c9af
Update tileable_rr_graph_gsb.cpp
Wang-Yuanqi-source Oct 22, 2024
9b8a3f2
Update tileable_rr_graph_gsb.h
Wang-Yuanqi-source Oct 22, 2024
ca9e9f1
Update tileable_rr_graph_node_builder.cpp
Wang-Yuanqi-source Oct 22, 2024
3f5633b
Update tileable_rr_graph_node_builder.h
Wang-Yuanqi-source Oct 22, 2024
317e2fe
Update vpr_utils.cpp
Wang-Yuanqi-source Oct 22, 2024
4b91e02
Update vpr_utils.h
Wang-Yuanqi-source Oct 22, 2024
0f34455
Update tileable_chan_details_builder.cpp
Wang-Yuanqi-source Oct 22, 2024
6ce3706
Merge branch 'master' into openfpga
tangxifan Oct 23, 2024
3937e3c
Merge branch 'openfpga' into patch-1
Wang-Yuanqi-source Oct 24, 2024
39c80f4
Merge branch 'master' into openfpga
tangxifan Oct 28, 2024
3a3f24e
Update tileable_rr_graph_gsb.cpp
Wang-Yuanqi-source Nov 4, 2024
a757254
Update rr_spatial_lookup.cpp
Wang-Yuanqi-source Nov 4, 2024
b447186
Update rr_gsb.cpp
Wang-Yuanqi-source Nov 4, 2024
35b4200
Update tileable_rr_graph_gsb.h
Wang-Yuanqi-source Nov 4, 2024
d5d2372
Update tileable_rr_graph_node_builder.cpp
Wang-Yuanqi-source Nov 4, 2024
8afea46
Update tileable_rr_graph_node_builder.h
Wang-Yuanqi-source Nov 4, 2024
1d45f3b
Update check_rr_graph.cpp
Wang-Yuanqi-source Nov 4, 2024
e8c88fa
Update check_rr_graph.h
Wang-Yuanqi-source Nov 4, 2024
7c6d85c
Update vib_inf.h
Wang-Yuanqi-source Nov 4, 2024
6075e31
Update physical_types.h
Wang-Yuanqi-source Nov 4, 2024
3941eef
Update vib_inf.cpp
Wang-Yuanqi-source Nov 4, 2024
6be2c9a
Update read_xml_arch_file.cpp
Wang-Yuanqi-source Nov 4, 2024
391d044
Update SetupVPR.cpp
Wang-Yuanqi-source Nov 4, 2024
6f681c2
Update SetupGrid.cpp
Wang-Yuanqi-source Nov 4, 2024
463bdd0
Update SetupGrid.h
Wang-Yuanqi-source Nov 4, 2024
6359b5c
Create SetupVibGrid.cpp
Wang-Yuanqi-source Nov 4, 2024
c0a2736
Create SetupVibGrid.h
Wang-Yuanqi-source Nov 4, 2024
52edaf9
Update vpr_api.cpp
Wang-Yuanqi-source Nov 4, 2024
60bc5a0
Update vpr_context.h
Wang-Yuanqi-source Nov 4, 2024
b9d587e
Update rr_graph.xsd
Wang-Yuanqi-source Nov 4, 2024
5ad2329
Update tileable_rr_graph_edge_builder.cpp
Wang-Yuanqi-source Nov 4, 2024
cbcdf0e
Update tileable_rr_graph_edge_builder.h
Wang-Yuanqi-source Nov 4, 2024
84faf43
Update rr_graph.cpp
Wang-Yuanqi-source Nov 4, 2024
4e046ef
Update rr_graph_uxsdcxx_serializer.h
Wang-Yuanqi-source Nov 4, 2024
60bee8f
Update overuse_report.cpp
Wang-Yuanqi-source Nov 4, 2024
0b4cfc2
Update router_lookahead_map.cpp
Wang-Yuanqi-source Nov 4, 2024
a182a76
Update router_lookahead_map_utils.cpp
Wang-Yuanqi-source Nov 4, 2024
6343061
Update rr_gsb.h
Wang-Yuanqi-source Nov 4, 2024
04959b7
Merge branch 'master' into openfpga
tangxifan Nov 4, 2024
fee1e52
Merge branch 'master' into openfpga
tangxifan Nov 12, 2024
d0f15b1
[lib] syntax
tangxifan Nov 13, 2024
6692776
[core] resolve conflicts
tangxifan Nov 13, 2024
8178b71
[lib] clang syntax
tangxifan Nov 13, 2024
3bb9068
Update tileable_rr_graph_node_builder.cpp
Wang-Yuanqi-source Nov 25, 2024
be709d2
Update SetupVibGrid.cpp
Wang-Yuanqi-source Nov 25, 2024
d7d93c9
Update tileable_rr_graph_node_builder.h
Wang-Yuanqi-source Nov 25, 2024
91960e2
Update tileable_rr_graph_builder.cpp
Wang-Yuanqi-source Nov 25, 2024
729ae80
Update tileable_rr_graph_edge_builder.cpp
Wang-Yuanqi-source Nov 25, 2024
7a0dfbc
Update tileable_rr_graph_gsb.cpp
Wang-Yuanqi-source Nov 25, 2024
2e50bfb
Update rr_gsb.h
Wang-Yuanqi-source Nov 25, 2024
9dac8c4
Update tileable_rr_graph_gsb.h
Wang-Yuanqi-source Nov 25, 2024
a4479e5
Update tileable_rr_graph_edge_builder.h
Wang-Yuanqi-source Nov 25, 2024
9ae8a99
Update vib_inf.h
Wang-Yuanqi-source Nov 25, 2024
230fe0f
Update vib_inf.cpp
Wang-Yuanqi-source Nov 25, 2024
1678907
Update tileable_rr_graph_gsb.cpp
Wang-Yuanqi-source Nov 25, 2024
cfe7c2a
Update index.rst
Wang-Yuanqi-source Nov 29, 2024
35a82e7
Create VIB.rst
Wang-Yuanqi-source Nov 29, 2024
e2fff38
Add files via upload
Wang-Yuanqi-source Nov 29, 2024
8dae0c3
Create vib_test_arch.xml
Wang-Yuanqi-source Nov 29, 2024
481efce
Create music.blif
Wang-Yuanqi-source Nov 29, 2024
9240ab6
Add files via upload
Wang-Yuanqi-source Nov 29, 2024
b96878a
Merge branch 'openfpga' into patch-1
Wang-Yuanqi-source Dec 17, 2024
fe31ad7
Merge pull request #2637 from Wang-Yuanqi-source/patch-1
tangxifan Jan 13, 2025
ed4faca
Merge branch 'master' into openfpga
tangxifan Jan 13, 2025
ec6da7f
[core] syntax
tangxifan Jan 13, 2025
bb5235e
[core] clang warning
tangxifan Jan 17, 2025
e438960
Merge branch 'master' of github.com:verilog-to-routing/vtr-verilog-to…
tangxifan Jan 17, 2025
0eb7de5
[core] clang warning
tangxifan Jan 17, 2025
6aa89f2
[core] compiler warning
tangxifan Jan 17, 2025
679a3b4
Merge branch 'master' into openfpga
tangxifan Jan 17, 2025
1959805
[core] clang syntax
tangxifan Jan 17, 2025
43d4422
Merge branch 'openfpga' of github.com:verilog-to-routing/vtr-verilog-…
tangxifan Jan 17, 2025
9e417cf
Update vib_test_arch.xml
Wang-Yuanqi-source Jan 18, 2025
27319b2
Create config.txt
Wang-Yuanqi-source Jan 18, 2025
364ac60
Create golden_results.txt
Wang-Yuanqi-source Jan 18, 2025
2f8191d
Update task_list.txt
Wang-Yuanqi-source Jan 18, 2025
4d881fa
Merge pull request #2869 from Wang-Yuanqi-source/patch-1
tangxifan Jan 27, 2025
d273cb2
Update VIB.rst
Wang-Yuanqi-source Feb 11, 2025
27bdc8c
Update VIB.rst
Wang-Yuanqi-source Feb 11, 2025
1eab1b3
Update VIB.rst
Wang-Yuanqi-source Feb 11, 2025
395d152
Update VIB.rst
Wang-Yuanqi-source Feb 11, 2025
1f7a845
Update VIB.rst
Wang-Yuanqi-source Feb 11, 2025
1d161b5
Update VIB.rst
Wang-Yuanqi-source Feb 11, 2025
393b6ce
Delete doc/src/Images/double-level.png
Wang-Yuanqi-source Feb 11, 2025
c699df9
Add files via upload
Wang-Yuanqi-source Feb 11, 2025
dca165c
Add files via upload
Wang-Yuanqi-source Feb 11, 2025
4a1a12f
Add files via upload
Wang-Yuanqi-source Feb 11, 2025
656471d
Update VIB.rst
Wang-Yuanqi-source Feb 11, 2025
2e9d87d
Update VIB.rst
Wang-Yuanqi-source Feb 11, 2025
d1d210e
Update VIB.rst
Wang-Yuanqi-source Feb 12, 2025
5ba8a0e
Update VIB.rst
Wang-Yuanqi-source Feb 12, 2025
4341b2b
Update VIB.rst
Wang-Yuanqi-source Feb 12, 2025
bf81263
Add files via upload
Wang-Yuanqi-source Feb 12, 2025
8fcd273
Rename example.png to vib_example.png
Wang-Yuanqi-source Feb 12, 2025
0468c29
Update VIB.rst
Wang-Yuanqi-source Feb 12, 2025
8c40b19
Update VIB.rst
Wang-Yuanqi-source Feb 12, 2025
579b136
Merge branch 'openfpga' into patch-1
tangxifan Mar 12, 2025
77df6c6
Merge pull request #2916 from Wang-Yuanqi-source/patch-1
tangxifan Mar 12, 2025
cab1db1
Update OpenFPGA (#2983)
amin1377 Apr 24, 2025
0f14bd9
Merge branch 'master' into openfpga
tangxifan Apr 24, 2025
2b664fe
[core] code format
tangxifan Apr 24, 2025
7950a1b
[core] remove blif benchmarks
tangxifan Apr 24, 2025
ba7b4a1
Update OpenFPGA (#3056)
amin1377 May 20, 2025
e71ef45
OpenFPGA Update (#3066)
amin1377 May 21, 2025
cc0302d
Update OpenFPGA (#3126)
amin1377 Jun 11, 2025
File filter

Filter by extension

Filter by extension


Conversations
Failed to load comments.
Loading
Jump to
The table of contents is too big for display.
Diff view
Diff view
  •  
  •  
  •  
2 changes: 2 additions & 0 deletions .github/scripts/hostsetup.sh
Original file line number Diff line number Diff line change
Expand Up @@ -70,6 +70,8 @@ apt install -y \
g++-9 \
gcc-9 \
wget \
openssl \
libssl-dev \
libtbb-dev

# installing the latest version of cmake
Expand Down
17 changes: 5 additions & 12 deletions .github/scripts/install_dependencies.sh
Original file line number Diff line number Diff line change
Expand Up @@ -2,40 +2,32 @@

sudo apt update

# Required packages specifically for the CI and not VTR in general.
sudo apt install -y \
autoconf \
automake \
bash \
bison \
binutils \
binutils-gold \
build-essential \
capnproto \
exuberant-ctags \
curl \
doxygen \
flex \
fontconfig \
gdb \
git \
gperf \
libcairo2-dev \
libcapnp-dev \
libgtk-3-dev \
libevent-dev \
libfontconfig1-dev \
liblist-moreutils-perl \
libncurses5-dev \
libx11-dev \
libxft-dev \
libxml2-utils \
libxml++2.6-dev \
libreadline-dev \
tcllib \
tcl8.6-dev \
libffi-dev \
perl \
pkg-config \
texinfo \
time \
valgrind \
Expand All @@ -54,9 +46,10 @@ sudo apt install -y \
clang-15 \
clang-16 \
clang-17 \
clang-18 \
clang-format-18 \
libtbb-dev
clang-18

# Standard packages install script.
./install_apt_packages.sh

pip install -r requirements.txt

Expand Down
17 changes: 5 additions & 12 deletions .github/scripts/install_jammy_dependencies.sh
Original file line number Diff line number Diff line change
Expand Up @@ -2,40 +2,32 @@

sudo apt update

# Required packages specifically for the CI and not VTR in general.
sudo apt install -y \
autoconf \
automake \
bash \
bison \
binutils \
binutils-gold \
build-essential \
capnproto \
exuberant-ctags \
curl \
doxygen \
flex \
fontconfig \
gdb \
git \
gperf \
libcairo2-dev \
libcapnp-dev \
libgtk-3-dev \
libevent-dev \
libfontconfig1-dev \
liblist-moreutils-perl \
libncurses5-dev \
libx11-dev \
libxft-dev \
libxml2-utils \
libxml++2.6-dev \
libreadline-dev \
tcllib \
tcl8.6-dev \
libffi-dev \
perl \
pkg-config \
texinfo \
time \
valgrind \
Expand All @@ -50,9 +42,10 @@ sudo apt install -y \
g++-11 \
gcc-11 \
g++-12 \
gcc-12 \
clang-format-14 \
libtbb-dev
gcc-12

# Standard packages install script.
./install_apt_packages.sh

pip install -r requirements.txt

Expand Down
10 changes: 10 additions & 0 deletions .github/workflows/nightly_test_manual.yml
Original file line number Diff line number Diff line change
Expand Up @@ -104,3 +104,13 @@ jobs:
run: |
source .venv/bin/activate
./run_reg_test.py -j12 vtr_reg_nightly_test7

- name: Upload regression results
if: success() || failure()
uses: actions/upload-artifact@v4
with:
name: nightly_test_results
path: |
vtr_flow/**/*.log
vtr_flow/**/vpr.out
vtr_flow/**/parse_results*.txt
10 changes: 10 additions & 0 deletions .github/workflows/stale.yml
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,11 @@ jobs:
steps:
- uses: actions/stale@v9
with:
# Set default number of days before being marked stale to 100 years
# This will be overriden by "days-before-issue-stale" and "days-before-pr-stale"
# This is done to avoid marking PRs as stale, as it is not something
# we want to do.
days-before-stale: 36500
# The message to be shown for stale issues
stale-issue-message: 'This issue has been inactive for a year and has been marked as stale. It will be closed in 15 days if it continues to be stale. If you believe this is still an issue, please add a comment.'
close-issue-message: 'This issue has been marked stale for 15 days and has been automatically closed.'
Expand All @@ -20,6 +25,11 @@ jobs:
# Start from the oldest issues
ascending: true

# Upper limit for number of API calls per day
# This worklfow does 2-3 API calls per issue
# including issues that have been marked stale
operations-per-run: 300

# The configuration below can be used to allow the same behaviour with PRs.
# Since we currently don't want to close old PRs, it is commented out but
# left here in case we change our mind.
Expand Down
124 changes: 87 additions & 37 deletions .github/workflows/test.yml
Original file line number Diff line number Diff line change
Expand Up @@ -99,7 +99,26 @@ jobs:
run: ./dev/${{ matrix.script }}


UniTests:
VerifyTestSuites:
runs-on: ubuntu-24.04
name: 'Verify Test Suites'
steps:

- uses: actions/setup-python@v5
with:
python-version: 3.12.3

- uses: actions/checkout@v4
# NOTE: We do not need sub-modules. This only verifies the tests, does not run them.

- name: 'Run test suite verification'
run: |
./dev/vtr_test_suite_verifier/verify_test_suites.py \
-vtr_regression_tests_dir vtr_flow/tasks/regression_tests \
-test_suite_info dev/vtr_test_suite_verifier/test_suites_info.json


UnitTests:
name: 'U: C++ Unit Tests'
runs-on: ubuntu-24.04
steps:
Expand All @@ -125,36 +144,90 @@ jobs:
run: ./.github/scripts/unittest.sh


Warnings:
name: 'W: Check Compilation Warnings'
# This test builds different variations of VTR (with different CMake Params)
# and ensures that they can run the basic regression tests. This also ensures
# that these build variations are warning clean.
BuildVariations:
runs-on: ubuntu-24.04
name: 'B: Build Variations'
env:
# For the CI, we want all build variations to be warning clean.
# NOTE: Need to turn IPO off due to false warnings being produced.
COMMON_CMAKE_PARAMS: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off'
steps:

- uses: actions/setup-python@v5
with:
python-version: 3.12.3

- uses: actions/checkout@v4
with:
submodules: 'true'

- name: Get number of CPU cores
- name: 'Get number of CPU cores'
uses: SimenB/github-actions-cpu-cores@v2
id: cpu-cores

- name: Install dependencies
- name: 'Install dependencies'
run: ./.github/scripts/install_dependencies.sh

- uses: hendrikmuhs/[email protected]
- name: 'ccache'
uses: hendrikmuhs/[email protected]

- name: Test
- name: 'Test with VTR_ASSERT_LEVEL 4'
if: success() || failure()
env:
#In order to get compilation warnings produced per source file, we must do a non-IPO build
#We also turn warnings into errors for this target by doing a strict compile
CMAKE_PARAMS: "-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_STRICT_COMPILE=on -DVTR_IPO_BUILD=off"
CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVTR_ASSERT_LEVEL=4"
NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
run: |
rm -f build/CMakeCache.txt
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
./.github/scripts/build.sh
make -j${{ steps.cpu-cores.outputs.count}}
./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}

- name: 'Test with NO_GRAPHICS'
if: success() || failure()
env:
CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVPR_USE_EZGL=off"
NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
run: |
rm -f build/CMakeCache.txt
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
make -j${{ steps.cpu-cores.outputs.count}}
./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}

- name: 'Test with NO_SERVER'
if: success() || failure()
env:
CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVPR_USE_SERVER=off"
NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
run: |
rm -f build/CMakeCache.txt
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
make -j${{ steps.cpu-cores.outputs.count}}
./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}

- name: 'Test with CAPNPROTO disabled'
if: success() || failure()
env:
CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVTR_ENABLE_CAPNPROTO=off"
NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
run: |
rm -f build/CMakeCache.txt
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
make -j${{ steps.cpu-cores.outputs.count}}
./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}

- name: 'Test with serial VPR_EXECUTION_ENGINE'
if: success() || failure()
env:
CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVPR_EXECUTION_ENGINE=serial -DTATUM_EXECUTION_ENGINE=serial"
NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
run: |
rm -f build/CMakeCache.txt
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
make -j${{ steps.cpu-cores.outputs.count}}
./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}


Regression:
Expand All @@ -169,36 +242,12 @@ jobs:
suite: 'vtr_reg_basic',
extra_pkgs: ""
},
{
name: 'Basic with highest assertion level',
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=4 -DWITH_BLIFEXPLORER=on',
suite: 'vtr_reg_basic',
extra_pkgs: ""
},
{
name: 'Basic_odin',
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DWITH_PARMYS=OFF -DWITH_ODIN=on',
suite: 'vtr_reg_basic_odin',
extra_pkgs: ""
},
{
name: 'Basic with NO_GRAPHICS',
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_USE_EZGL=off',
suite: 'vtr_reg_basic',
extra_pkgs: ""
},
{
name: 'Basic with NO_SERVER',
params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_USE_EZGL=on -DVPR_USE_SERVER=off',
suite: 'vtr_reg_basic',
extra_pkgs: ""
},
{
name: 'Basic with CAPNPROTO disabled',
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_CAPNPROTO=off',
suite: 'vtr_reg_basic',
extra_pkgs: ""
},
{
name: 'Basic with VTR_ENABLE_DEBUG_LOGGING',
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_DEBUG_LOGGING=on',
Expand Down Expand Up @@ -510,8 +559,9 @@ jobs:
needs:
- Build
- Format
- UniTests
- Warnings
- VerifyTestSuites
- UnitTests
- BuildVariations
- Regression
- Sanitized
- Parmys
Expand Down
4 changes: 4 additions & 0 deletions .gitmodules
Original file line number Diff line number Diff line change
Expand Up @@ -6,3 +6,7 @@
[submodule "libs/EXTERNAL/sockpp"]
path = libs/EXTERNAL/sockpp
url = https://github.com/w0lek/sockpp.git

[submodule "libs/EXTERNAL/libezgl"]
path = libs/EXTERNAL/libezgl
url = https://github.com/verilog-to-routing/ezgl.git
4 changes: 4 additions & 0 deletions .readthedocs.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,10 @@ build:
tools:
python: "3.11"

submodules:
include: all

python:
install:
- requirements: doc/requirements.txt
- requirements: requirements.txt
5 changes: 1 addition & 4 deletions CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -26,11 +26,11 @@ set_property(CACHE VTR_IPO_BUILD PROPERTY STRINGS auto on off)
set(VTR_ASSERT_LEVEL "2" CACHE STRING "VTR assertion checking level. 0: no assertions, 1: fast assertions, 2: regular assertions, 3: additional assertions with noticeable run-time overhead, 4: all assertions (including those with significant run-time cost)")
set_property(CACHE VTR_ASSERT_LEVEL PROPERTY STRINGS 0 1 2 3 4)

option(VTR_ENABLE_STRICT_COMPILE "Specifies whether compiler warnings should be treated as errors (e.g. -Werror)" OFF)
option(VTR_ENABLE_SANITIZE "Enable address/leak/undefined-behaviour sanitizers (i.e. run-time error checking)" OFF)
option(VTR_ENABLE_PROFILING "Enable performance profiler (gprof)" OFF)
option(VTR_ENABLE_COVERAGE "Enable code coverage tracking (gcov)" OFF)
option(VTR_ENABLE_DEBUG_LOGGING "Enable debug logging" OFF)
option(VTR_ENABLE_VERSION "Enable version number up-to-date during compilation" ON)
option(VTR_ENABLE_VERBOSE "Enable increased debug verbosity" OFF)
option(SPEC_CPU "Enable SPEC CPU v8 support" OFF)

Expand All @@ -42,9 +42,6 @@ option(VTR_ENABLE_CAPNPROTO "Enable capnproto binary serialization support in VP
#Allow the user to decide whether to compile the server module
option(VPR_USE_SERVER "Specify whether vpr enables the server mode" ON)

#Allow the user to enable/disable VPR analytic placement
#VPR option --enable_analytic_placer is also required for Analytic Placement
option(VPR_ANALYTIC_PLACE "Enable analytic placement in VPR." ON)
option(VPR_ENABLE_INTERCHANGE "Enable FPGA interchange." ON)
option(VPR_ENABLE_NOC_SAT_ROUTING "Enable NoC SAT routing." OFF)

Expand Down
Loading