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Merge pull request #2138 from antmicro/move-unconnected-wire-declaration
Declare unconnected wires before cell instances
2 parents 2f34458 + 8d9b0e4 commit 6d760c4

7 files changed

+98
-71
lines changed

‎vpr/src/base/netlist_writer.cpp

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -961,15 +961,15 @@ class NetlistWriterVisitor : public NetlistVisitor {
961961
}
962962
}
963963

964-
//All the cell instances
964+
//All the cell instances (to an internal buffer for now)
965+
std::stringstream instances_ss;
966+
965967
size_t unconn_count = 0;
966-
verilog_os_ << "\n";
967-
verilog_os_ << indent(depth + 1) << "//Cell instances\n";
968968
for (auto& inst : cell_instances_) {
969-
inst->print_verilog(verilog_os_, unconn_count, depth + 1);
969+
inst->print_verilog(instances_ss, unconn_count, depth + 1);
970970
}
971971

972-
//Unconnected wires
972+
//Unconnected wires declarations
973973
if (unconn_count) {
974974
verilog_os_ << "\n";
975975
verilog_os_ << indent(depth + 1) << "//Unconnected wires\n";
@@ -979,6 +979,11 @@ class NetlistWriterVisitor : public NetlistVisitor {
979979
}
980980
}
981981

982+
//All the cell instances
983+
verilog_os_ << "\n";
984+
verilog_os_ << indent(depth + 1) << "//Cell instances\n";
985+
verilog_os_ << instances_ss.str();
986+
982987
verilog_os_ << "\n";
983988
verilog_os_ << indent(depth) << "endmodule\n";
984989
}

‎vpr/test/test_post_verilog.cpp

Lines changed: 27 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -76,21 +76,43 @@ void compare_files(const std::string& output_fname, const std::string& golden_fn
7676
REQUIRE(output_data == golden_data);
7777
}
7878

79+
void copy_file(const std::string& src_fname, const std::string& dst_fname) {
80+
std::ifstream src_file(src_fname, std::ios::binary);
81+
std::ofstream dst_file(dst_fname, std::ios::binary);
82+
83+
REQUIRE(src_file.good());
84+
REQUIRE(dst_file.good());
85+
86+
src_file.seekg(0, std::ios_base::end);
87+
size_t size = src_file.tellg();
88+
src_file.seekg(0, std::ios_base::beg);
89+
90+
auto buf = std::unique_ptr<uint8_t>(new uint8_t[size]);
91+
src_file.read((char*)buf.get(), size);
92+
dst_file.write((char*)buf.get(), size);
93+
}
94+
7995
TEST_CASE("post_verilog", "[vpr]") {
8096
do_vpr_flow("unconnected", "unconnected");
81-
compare_files("unconnected_post_synthesis.v", "test_post_verilog_i_unconnected_o_unconnected.golden.v");
97+
copy_file("unconnected_post_synthesis.v", "test_post_verilog_i_unconnected_o_unconnected.out.v");
8298

8399
do_vpr_flow("unconnected", "nets");
84-
compare_files("unconnected_post_synthesis.v", "test_post_verilog_i_unconnected_o_nets.golden.v");
100+
copy_file("unconnected_post_synthesis.v", "test_post_verilog_i_unconnected_o_nets.out.v");
85101

86102
do_vpr_flow("vcc", "unconnected");
87-
compare_files("unconnected_post_synthesis.v", "test_post_verilog_i_vcc_o_unconnected.golden.v");
103+
copy_file("unconnected_post_synthesis.v", "test_post_verilog_i_vcc_o_unconnected.out.v");
88104

89105
do_vpr_flow("gnd", "unconnected");
90-
compare_files("unconnected_post_synthesis.v", "test_post_verilog_i_gnd_o_unconnected.golden.v");
106+
copy_file("unconnected_post_synthesis.v", "test_post_verilog_i_gnd_o_unconnected.out.v");
91107

92108
do_vpr_flow("nets", "unconnected");
93-
compare_files("unconnected_post_synthesis.v", "test_post_verilog_i_nets_o_unconnected.golden.v");
109+
copy_file("unconnected_post_synthesis.v", "test_post_verilog_i_nets_o_unconnected.out.v");
110+
111+
compare_files("test_post_verilog_i_unconnected_o_unconnected.out.v", "test_post_verilog_i_unconnected_o_unconnected.golden.v");
112+
compare_files("test_post_verilog_i_unconnected_o_nets.out.v", "test_post_verilog_i_unconnected_o_nets.golden.v");
113+
compare_files("test_post_verilog_i_vcc_o_unconnected.out.v", "test_post_verilog_i_vcc_o_unconnected.golden.v");
114+
compare_files("test_post_verilog_i_gnd_o_unconnected.out.v", "test_post_verilog_i_gnd_o_unconnected.golden.v");
115+
compare_files("test_post_verilog_i_nets_o_unconnected.out.v", "test_post_verilog_i_nets_o_unconnected.golden.v");
94116
}
95117

96118
} // namespace

‎vpr/test/test_post_verilog_i_gnd_o_unconnected.golden.v

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
//Verilog generated by VPR 8.1.0-dev+5de140b68 from post-place-and-route implementation
1+
//Verilog generated by VPR 8.1.0-dev+684ecc193 from post-place-and-route implementation
22
module unconnected (
33
input \a[0] ,
44
input \a[1] ,
@@ -188,6 +188,16 @@ module unconnected (
188188
);
189189

190190

191+
//Unconnected wires
192+
wire \__vpr__unconn0 ;
193+
wire \__vpr__unconn1 ;
194+
wire \__vpr__unconn2 ;
195+
wire \__vpr__unconn3 ;
196+
wire \__vpr__unconn4 ;
197+
wire \__vpr__unconn5 ;
198+
wire \__vpr__unconn6 ;
199+
wire \__vpr__unconn7 ;
200+
191201
//Cell instances
192202
dsp #(
193203
) \dsp_inst (
@@ -234,14 +244,4 @@ module unconnected (
234244
);
235245

236246

237-
//Unconnected wires
238-
wire \__vpr__unconn0 ;
239-
wire \__vpr__unconn1 ;
240-
wire \__vpr__unconn2 ;
241-
wire \__vpr__unconn3 ;
242-
wire \__vpr__unconn4 ;
243-
wire \__vpr__unconn5 ;
244-
wire \__vpr__unconn6 ;
245-
wire \__vpr__unconn7 ;
246-
247247
endmodule

‎vpr/test/test_post_verilog_i_nets_o_unconnected.golden.v

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
//Verilog generated by VPR 8.1.0-dev+5de140b68 from post-place-and-route implementation
1+
//Verilog generated by VPR 8.1.0-dev+684ecc193 from post-place-and-route implementation
22
module unconnected (
33
input \a[0] ,
44
input \a[1] ,
@@ -188,6 +188,21 @@ module unconnected (
188188
);
189189

190190

191+
//Unconnected wires
192+
wire \__vpr__unconn0 ;
193+
wire \__vpr__unconn1 ;
194+
wire \__vpr__unconn2 ;
195+
wire \__vpr__unconn3 ;
196+
wire \__vpr__unconn4 ;
197+
wire \__vpr__unconn5 ;
198+
wire \__vpr__unconn6 ;
199+
wire \__vpr__unconn7 ;
200+
wire \__vpr__unconn8 ;
201+
wire \__vpr__unconn9 ;
202+
wire \__vpr__unconn10 ;
203+
wire \__vpr__unconn11 ;
204+
wire \__vpr__unconn12 ;
205+
191206
//Cell instances
192207
dsp #(
193208
) \dsp_inst (
@@ -234,19 +249,4 @@ module unconnected (
234249
);
235250

236251

237-
//Unconnected wires
238-
wire \__vpr__unconn0 ;
239-
wire \__vpr__unconn1 ;
240-
wire \__vpr__unconn2 ;
241-
wire \__vpr__unconn3 ;
242-
wire \__vpr__unconn4 ;
243-
wire \__vpr__unconn5 ;
244-
wire \__vpr__unconn6 ;
245-
wire \__vpr__unconn7 ;
246-
wire \__vpr__unconn8 ;
247-
wire \__vpr__unconn9 ;
248-
wire \__vpr__unconn10 ;
249-
wire \__vpr__unconn11 ;
250-
wire \__vpr__unconn12 ;
251-
252252
endmodule

‎vpr/test/test_post_verilog_i_unconnected_o_nets.golden.v

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
//Verilog generated by VPR 8.1.0-dev+5de140b68 from post-place-and-route implementation
1+
//Verilog generated by VPR 8.1.0-dev+684ecc193 from post-place-and-route implementation
22
module unconnected (
33
input \a[0] ,
44
input \a[1] ,
@@ -188,6 +188,17 @@ module unconnected (
188188
);
189189

190190

191+
//Unconnected wires
192+
wire \__vpr__unconn0 ;
193+
wire \__vpr__unconn1 ;
194+
wire \__vpr__unconn2 ;
195+
wire \__vpr__unconn3 ;
196+
wire \__vpr__unconn4 ;
197+
wire \__vpr__unconn5 ;
198+
wire \__vpr__unconn6 ;
199+
wire \__vpr__unconn7 ;
200+
wire \__vpr__unconn8 ;
201+
191202
//Cell instances
192203
dsp #(
193204
) \dsp_inst (
@@ -234,15 +245,4 @@ module unconnected (
234245
);
235246

236247

237-
//Unconnected wires
238-
wire \__vpr__unconn0 ;
239-
wire \__vpr__unconn1 ;
240-
wire \__vpr__unconn2 ;
241-
wire \__vpr__unconn3 ;
242-
wire \__vpr__unconn4 ;
243-
wire \__vpr__unconn5 ;
244-
wire \__vpr__unconn6 ;
245-
wire \__vpr__unconn7 ;
246-
wire \__vpr__unconn8 ;
247-
248248
endmodule

‎vpr/test/test_post_verilog_i_unconnected_o_unconnected.golden.v

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
//Verilog generated by VPR 8.1.0-dev+5de140b68 from post-place-and-route implementation
1+
//Verilog generated by VPR 8.1.0-dev+684ecc193 from post-place-and-route implementation
22
module unconnected (
33
input \a[0] ,
44
input \a[1] ,
@@ -188,6 +188,16 @@ module unconnected (
188188
);
189189

190190

191+
//Unconnected wires
192+
wire \__vpr__unconn0 ;
193+
wire \__vpr__unconn1 ;
194+
wire \__vpr__unconn2 ;
195+
wire \__vpr__unconn3 ;
196+
wire \__vpr__unconn4 ;
197+
wire \__vpr__unconn5 ;
198+
wire \__vpr__unconn6 ;
199+
wire \__vpr__unconn7 ;
200+
191201
//Cell instances
192202
dsp #(
193203
) \dsp_inst (
@@ -234,14 +244,4 @@ module unconnected (
234244
);
235245

236246

237-
//Unconnected wires
238-
wire \__vpr__unconn0 ;
239-
wire \__vpr__unconn1 ;
240-
wire \__vpr__unconn2 ;
241-
wire \__vpr__unconn3 ;
242-
wire \__vpr__unconn4 ;
243-
wire \__vpr__unconn5 ;
244-
wire \__vpr__unconn6 ;
245-
wire \__vpr__unconn7 ;
246-
247247
endmodule

‎vpr/test/test_post_verilog_i_vcc_o_unconnected.golden.v

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
//Verilog generated by VPR 8.1.0-dev+5de140b68 from post-place-and-route implementation
1+
//Verilog generated by VPR 8.1.0-dev+684ecc193 from post-place-and-route implementation
22
module unconnected (
33
input \a[0] ,
44
input \a[1] ,
@@ -188,6 +188,16 @@ module unconnected (
188188
);
189189

190190

191+
//Unconnected wires
192+
wire \__vpr__unconn0 ;
193+
wire \__vpr__unconn1 ;
194+
wire \__vpr__unconn2 ;
195+
wire \__vpr__unconn3 ;
196+
wire \__vpr__unconn4 ;
197+
wire \__vpr__unconn5 ;
198+
wire \__vpr__unconn6 ;
199+
wire \__vpr__unconn7 ;
200+
191201
//Cell instances
192202
dsp #(
193203
) \dsp_inst (
@@ -234,14 +244,4 @@ module unconnected (
234244
);
235245

236246

237-
//Unconnected wires
238-
wire \__vpr__unconn0 ;
239-
wire \__vpr__unconn1 ;
240-
wire \__vpr__unconn2 ;
241-
wire \__vpr__unconn3 ;
242-
wire \__vpr__unconn4 ;
243-
wire \__vpr__unconn5 ;
244-
wire \__vpr__unconn6 ;
245-
wire \__vpr__unconn7 ;
246-
247247
endmodule

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