Updated golden results for post-synthesis Verilog netlist output

Signed-off-by: Maciej Kurc <[email protected]>

Author: mkurc-ant

vpr/test/test_post_verilog_i_gnd_o_unconnected.golden.v

@@ -1,4 +1,4 @@
-//Verilog generated by VPR 8.1.0-dev+5de140b68 from post-place-and-route implementation
+//Verilog generated by VPR 8.1.0-dev+684ecc193 from post-place-and-route implementation
 module unconnected (
     input \a[0] ,
     input \a[1] ,
@@ -188,6 +188,16 @@ module unconnected (
     );
 
 
+    //Unconnected wires
+    wire \__vpr__unconn0 ;
+    wire \__vpr__unconn1 ;
+    wire \__vpr__unconn2 ;
+    wire \__vpr__unconn3 ;
+    wire \__vpr__unconn4 ;
+    wire \__vpr__unconn5 ;
+    wire \__vpr__unconn6 ;
+    wire \__vpr__unconn7 ;
+
     //Cell instances
     dsp #(
     ) \dsp_inst  (
@@ -234,14 +244,4 @@ module unconnected (
     );
 
 
-    //Unconnected wires
-    wire \__vpr__unconn0 ;
-    wire \__vpr__unconn1 ;
-    wire \__vpr__unconn2 ;
-    wire \__vpr__unconn3 ;
-    wire \__vpr__unconn4 ;
-    wire \__vpr__unconn5 ;
-    wire \__vpr__unconn6 ;
-    wire \__vpr__unconn7 ;
-
 endmodule

vpr/test/test_post_verilog_i_nets_o_unconnected.golden.v

@@ -1,4 +1,4 @@
-//Verilog generated by VPR 8.1.0-dev+5de140b68 from post-place-and-route implementation
+//Verilog generated by VPR 8.1.0-dev+684ecc193 from post-place-and-route implementation
 module unconnected (
     input \a[0] ,
     input \a[1] ,
@@ -188,6 +188,21 @@ module unconnected (
     );
 
 
+    //Unconnected wires
+    wire \__vpr__unconn0 ;
+    wire \__vpr__unconn1 ;
+    wire \__vpr__unconn2 ;
+    wire \__vpr__unconn3 ;
+    wire \__vpr__unconn4 ;
+    wire \__vpr__unconn5 ;
+    wire \__vpr__unconn6 ;
+    wire \__vpr__unconn7 ;
+    wire \__vpr__unconn8 ;
+    wire \__vpr__unconn9 ;
+    wire \__vpr__unconn10 ;
+    wire \__vpr__unconn11 ;
+    wire \__vpr__unconn12 ;
+
     //Cell instances
     dsp #(
     ) \dsp_inst  (
@@ -234,19 +249,4 @@ module unconnected (
     );
 
 
-    //Unconnected wires
-    wire \__vpr__unconn0 ;
-    wire \__vpr__unconn1 ;
-    wire \__vpr__unconn2 ;
-    wire \__vpr__unconn3 ;
-    wire \__vpr__unconn4 ;
-    wire \__vpr__unconn5 ;
-    wire \__vpr__unconn6 ;
-    wire \__vpr__unconn7 ;
-    wire \__vpr__unconn8 ;
-    wire \__vpr__unconn9 ;
-    wire \__vpr__unconn10 ;
-    wire \__vpr__unconn11 ;
-    wire \__vpr__unconn12 ;
-
 endmodule

vpr/test/test_post_verilog_i_unconnected_o_nets.golden.v

@@ -1,4 +1,4 @@
-//Verilog generated by VPR 8.1.0-dev+5de140b68 from post-place-and-route implementation
+//Verilog generated by VPR 8.1.0-dev+684ecc193 from post-place-and-route implementation
 module unconnected (
     input \a[0] ,
     input \a[1] ,
@@ -188,6 +188,17 @@ module unconnected (
     );
 
 
+    //Unconnected wires
+    wire \__vpr__unconn0 ;
+    wire \__vpr__unconn1 ;
+    wire \__vpr__unconn2 ;
+    wire \__vpr__unconn3 ;
+    wire \__vpr__unconn4 ;
+    wire \__vpr__unconn5 ;
+    wire \__vpr__unconn6 ;
+    wire \__vpr__unconn7 ;
+    wire \__vpr__unconn8 ;
+
     //Cell instances
     dsp #(
     ) \dsp_inst  (
@@ -234,15 +245,4 @@ module unconnected (
     );
 
 
-    //Unconnected wires
-    wire \__vpr__unconn0 ;
-    wire \__vpr__unconn1 ;
-    wire \__vpr__unconn2 ;
-    wire \__vpr__unconn3 ;
-    wire \__vpr__unconn4 ;
-    wire \__vpr__unconn5 ;
-    wire \__vpr__unconn6 ;
-    wire \__vpr__unconn7 ;
-    wire \__vpr__unconn8 ;
-
 endmodule

vpr/test/test_post_verilog_i_unconnected_o_unconnected.golden.v

@@ -1,4 +1,4 @@
-//Verilog generated by VPR 8.1.0-dev+5de140b68 from post-place-and-route implementation
+//Verilog generated by VPR 8.1.0-dev+684ecc193 from post-place-and-route implementation
 module unconnected (
     input \a[0] ,
     input \a[1] ,
@@ -188,6 +188,16 @@ module unconnected (
     );
 
 
+    //Unconnected wires
+    wire \__vpr__unconn0 ;
+    wire \__vpr__unconn1 ;
+    wire \__vpr__unconn2 ;
+    wire \__vpr__unconn3 ;
+    wire \__vpr__unconn4 ;
+    wire \__vpr__unconn5 ;
+    wire \__vpr__unconn6 ;
+    wire \__vpr__unconn7 ;
+
     //Cell instances
     dsp #(
     ) \dsp_inst  (
@@ -234,14 +244,4 @@ module unconnected (
     );
 
 
-    //Unconnected wires
-    wire \__vpr__unconn0 ;
-    wire \__vpr__unconn1 ;
-    wire \__vpr__unconn2 ;
-    wire \__vpr__unconn3 ;
-    wire \__vpr__unconn4 ;
-    wire \__vpr__unconn5 ;
-    wire \__vpr__unconn6 ;
-    wire \__vpr__unconn7 ;
-
 endmodule

vpr/test/test_post_verilog_i_vcc_o_unconnected.golden.v

@@ -1,4 +1,4 @@
-//Verilog generated by VPR 8.1.0-dev+5de140b68 from post-place-and-route implementation
+//Verilog generated by VPR 8.1.0-dev+684ecc193 from post-place-and-route implementation
 module unconnected (
     input \a[0] ,
     input \a[1] ,
@@ -188,6 +188,16 @@ module unconnected (
     );
 
 
+    //Unconnected wires
+    wire \__vpr__unconn0 ;
+    wire \__vpr__unconn1 ;
+    wire \__vpr__unconn2 ;
+    wire \__vpr__unconn3 ;
+    wire \__vpr__unconn4 ;
+    wire \__vpr__unconn5 ;
+    wire \__vpr__unconn6 ;
+    wire \__vpr__unconn7 ;
+
     //Cell instances
     dsp #(
     ) \dsp_inst  (
@@ -234,14 +244,4 @@ module unconnected (
     );
 
 
-    //Unconnected wires
-    wire \__vpr__unconn0 ;
-    wire \__vpr__unconn1 ;
-    wire \__vpr__unconn2 ;
-    wire \__vpr__unconn3 ;
-    wire \__vpr__unconn4 ;
-    wire \__vpr__unconn5 ;
-    wire \__vpr__unconn6 ;
-    wire \__vpr__unconn7 ;
-
 endmodule