A CPU implemented in a modular synthesizer
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Mar 20, 2022
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processor-design
Here are 95 public repositories matching this topic...
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…
cpu processor simd verilog alu adder instruction-set-architecture cadence-virtuoso multiplier verilog-project processor-design
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Jul 17, 2022 - Verilog
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.
processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design
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Jun 5, 2025 - SystemVerilog
tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
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Jul 14, 2021 - SystemVerilog
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
assembly assembler verilog computer-architecture instruction-set-architecture computer-organization hardware-description-language processor-design single-cycle-processor
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Dec 7, 2024 - Verilog
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
processor-architecture cpu vhdl isa cpu-model instruction-set-architecture mips-processor vhdl-modules risc-processor vhdl-code cpu-architecture multi-cycle processor-design
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Jun 19, 2021 - VHDL
Chisel implementation of Neural Processing Unit for System on the Chip
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Aug 29, 2025 - Scala
EE577b-Course-Project
verilog-hdl multiprocessor processor-design networkonchip synopsys-dc cadence-ncverilog cadence-conformal
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May 6, 2020 - Verilog
CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>
computer-science processor-architecture engineering computer-engineering textbooks computer-organization computer-organisation processor-design computer-organisation-architechure computer-organization-lab computer-organization-and-design computer-organ ameythakur amey megasatish
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Mar 13, 2024 - C
Design and verification of a simple pipelined RISC processor in Verilog, featuring a five-stage pipeline and custom ISA.
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Jul 15, 2024 - Verilog
Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.
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Oct 5, 2025 - VHDL
Implementation of Vector Reduce Min and Vector Negation ASIC Hardware, plus a toy CPU, memory and custom ISA for demo. Can be compiled to Verilog. Demos include fib series computations using custom ISA (and custom assembly) and some vector programs.
processor-architecture ram hardware processor bus bluespec hardware-designs vlsi hardware-acceleration vlsi-physical-design bluespec-systemverilog processor-design vector-processor vlsi-design bluespec-systemverilog-language vlsi-cad
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Jan 11, 2021 - Bluespec
A simple processor designed using Verilog and Altera DE1 development board.
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Apr 22, 2020 - Verilog
NanoGo a Go (golang) Subset for Homebrew / Hobby CPUs
go golang cpu compiler assembly hobby-project hobby-compiler processor-design hobby-language homebrew-computer
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Jan 8, 2024 - Go
Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. It supports the complete RV32I instruction set (R, I, S, B, U, J types).
fpga vivado computer-architecture system-verilog risc-v cpu-architecture processor-design single-cycle-processor digital-design-and-computer-organization rv32i-processor
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Jul 21, 2025 - SystemVerilog
SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU
processor-architecture cpu processor computer-architecture digital-design computer-organization processor-design processor-simulation
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Aug 31, 2021 - Assembly
🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.
computer-science cpu fpga processor riscv verilog computer-architecture hdl soc verilog-hdl risc-v soft-core rv32i system-on-chip riscv32 dhrystone rv32 processor-design basic-rv32s risc-v-learn
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Oct 12, 2025 - Verilog
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