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python: Apply Black formatter to Python files
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The command executed was `black src configs tests util`.

Change-Id: I8dfaa6ab04658fea37618127d6ac19270028d771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47024
Maintainer: Bobby Bruce <[email protected]>
Reviewed-by: Jason Lowe-Power <[email protected]>
Reviewed-by: Giacomo Travaglini <[email protected]>
Tested-by: kokoro <[email protected]>
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@BobbyRBruce @giactra
BobbyRBruce authored and giactra committed Aug 3, 2022
1 parent 1cfaa8d commit 787204c
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171 changes: 109 additions & 62 deletions configs/common/Benchmarks.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,9 +28,11 @@
from os import environ as env
from m5.defines import buildEnv


class SysConfig:
def __init__(self, script=None, mem=None, disks=None, rootdev=None,
os_type='linux'):
def __init__(
self, script=None, mem=None, disks=None, rootdev=None, os_type="linux"
):
self.scriptname = script
self.disknames = disks
self.memsize = mem
Expand All @@ -41,13 +43,13 @@ def script(self):
if self.scriptname:
return script(self.scriptname)
else:
return ''
return ""

def mem(self):
if self.memsize:
return self.memsize
else:
return '128MB'
return "128MB"

def disks(self):
if self.disknames:
Expand All @@ -59,72 +61,117 @@ def rootdev(self):
if self.root:
return self.root
else:
return '/dev/sda1'
return "/dev/sda1"

def os_type(self):
return self.ostype


# Benchmarks are defined as a key in a dict which is a list of SysConfigs
# The first defined machine is the test system, the others are driving systems

Benchmarks = {
'PovrayBench': [SysConfig('povray-bench.rcS', '512MB', ['povray.img'])],
'PovrayAutumn': [SysConfig('povray-autumn.rcS', '512MB', ['povray.img'])],

'NetperfStream': [SysConfig('netperf-stream-client.rcS'),
SysConfig('netperf-server.rcS')],
'NetperfStreamUdp': [SysConfig('netperf-stream-udp-client.rcS'),
SysConfig('netperf-server.rcS')],
'NetperfUdpLocal': [SysConfig('netperf-stream-udp-local.rcS')],
'NetperfStreamNT': [SysConfig('netperf-stream-nt-client.rcS'),
SysConfig('netperf-server.rcS')],
'NetperfMaerts': [SysConfig('netperf-maerts-client.rcS'),
SysConfig('netperf-server.rcS')],
'SurgeStandard': [SysConfig('surge-server.rcS', '512MB'),
SysConfig('surge-client.rcS', '256MB')],
'SurgeSpecweb': [SysConfig('spec-surge-server.rcS', '512MB'),
SysConfig('spec-surge-client.rcS', '256MB')],
'Nhfsstone': [SysConfig('nfs-server-nhfsstone.rcS', '512MB'),
SysConfig('nfs-client-nhfsstone.rcS')],
'Nfs': [SysConfig('nfs-server.rcS', '900MB'),
SysConfig('nfs-client-dbench.rcS')],
'NfsTcp': [SysConfig('nfs-server.rcS', '900MB'),
SysConfig('nfs-client-tcp.rcS')],
'IScsiInitiator': [SysConfig('iscsi-client.rcS', '512MB'),
SysConfig('iscsi-server.rcS', '512MB')],
'IScsiTarget': [SysConfig('iscsi-server.rcS', '512MB'),
SysConfig('iscsi-client.rcS', '512MB')],
'Validation': [SysConfig('iscsi-server.rcS', '512MB'),
SysConfig('iscsi-client.rcS', '512MB')],
'Ping': [SysConfig('ping-server.rcS',),
SysConfig('ping-client.rcS')],

'ValAccDelay': [SysConfig('devtime.rcS', '512MB')],
'ValAccDelay2': [SysConfig('devtimewmr.rcS', '512MB')],
'ValMemLat': [SysConfig('micro_memlat.rcS', '512MB')],
'ValMemLat2MB': [SysConfig('micro_memlat2mb.rcS', '512MB')],
'ValMemLat8MB': [SysConfig('micro_memlat8mb.rcS', '512MB')],
'ValMemLat': [SysConfig('micro_memlat8.rcS', '512MB')],
'ValTlbLat': [SysConfig('micro_tlblat.rcS', '512MB')],
'ValSysLat': [SysConfig('micro_syscall.rcS', '512MB')],
'ValCtxLat': [SysConfig('micro_ctx.rcS', '512MB')],
'ValStream': [SysConfig('micro_stream.rcS', '512MB')],
'ValStreamScale': [SysConfig('micro_streamscale.rcS', '512MB')],
'ValStreamCopy': [SysConfig('micro_streamcopy.rcS', '512MB')],

'MutexTest': [SysConfig('mutex-test.rcS', '128MB')],
'ArmAndroid-GB': [SysConfig('null.rcS', '256MB',
['ARMv7a-Gingerbread-Android.SMP.mouse.nolock.clean.img'],
None, 'android-gingerbread')],
'bbench-gb': [SysConfig('bbench-gb.rcS', '256MB',
['ARMv7a-Gingerbread-Android.SMP.mouse.nolock.img'],
None, 'android-gingerbread')],
'ArmAndroid-ICS': [SysConfig('null.rcS', '256MB',
['ARMv7a-ICS-Android.SMP.nolock.clean.img'],
None, 'android-ics')],
'bbench-ics': [SysConfig('bbench-ics.rcS', '256MB',
['ARMv7a-ICS-Android.SMP.nolock.img'],
None, 'android-ics')]
"PovrayBench": [SysConfig("povray-bench.rcS", "512MB", ["povray.img"])],
"PovrayAutumn": [SysConfig("povray-autumn.rcS", "512MB", ["povray.img"])],
"NetperfStream": [
SysConfig("netperf-stream-client.rcS"),
SysConfig("netperf-server.rcS"),
],
"NetperfStreamUdp": [
SysConfig("netperf-stream-udp-client.rcS"),
SysConfig("netperf-server.rcS"),
],
"NetperfUdpLocal": [SysConfig("netperf-stream-udp-local.rcS")],
"NetperfStreamNT": [
SysConfig("netperf-stream-nt-client.rcS"),
SysConfig("netperf-server.rcS"),
],
"NetperfMaerts": [
SysConfig("netperf-maerts-client.rcS"),
SysConfig("netperf-server.rcS"),
],
"SurgeStandard": [
SysConfig("surge-server.rcS", "512MB"),
SysConfig("surge-client.rcS", "256MB"),
],
"SurgeSpecweb": [
SysConfig("spec-surge-server.rcS", "512MB"),
SysConfig("spec-surge-client.rcS", "256MB"),
],
"Nhfsstone": [
SysConfig("nfs-server-nhfsstone.rcS", "512MB"),
SysConfig("nfs-client-nhfsstone.rcS"),
],
"Nfs": [
SysConfig("nfs-server.rcS", "900MB"),
SysConfig("nfs-client-dbench.rcS"),
],
"NfsTcp": [
SysConfig("nfs-server.rcS", "900MB"),
SysConfig("nfs-client-tcp.rcS"),
],
"IScsiInitiator": [
SysConfig("iscsi-client.rcS", "512MB"),
SysConfig("iscsi-server.rcS", "512MB"),
],
"IScsiTarget": [
SysConfig("iscsi-server.rcS", "512MB"),
SysConfig("iscsi-client.rcS", "512MB"),
],
"Validation": [
SysConfig("iscsi-server.rcS", "512MB"),
SysConfig("iscsi-client.rcS", "512MB"),
],
"Ping": [SysConfig("ping-server.rcS"), SysConfig("ping-client.rcS")],
"ValAccDelay": [SysConfig("devtime.rcS", "512MB")],
"ValAccDelay2": [SysConfig("devtimewmr.rcS", "512MB")],
"ValMemLat": [SysConfig("micro_memlat.rcS", "512MB")],
"ValMemLat2MB": [SysConfig("micro_memlat2mb.rcS", "512MB")],
"ValMemLat8MB": [SysConfig("micro_memlat8mb.rcS", "512MB")],
"ValMemLat": [SysConfig("micro_memlat8.rcS", "512MB")],
"ValTlbLat": [SysConfig("micro_tlblat.rcS", "512MB")],
"ValSysLat": [SysConfig("micro_syscall.rcS", "512MB")],
"ValCtxLat": [SysConfig("micro_ctx.rcS", "512MB")],
"ValStream": [SysConfig("micro_stream.rcS", "512MB")],
"ValStreamScale": [SysConfig("micro_streamscale.rcS", "512MB")],
"ValStreamCopy": [SysConfig("micro_streamcopy.rcS", "512MB")],
"MutexTest": [SysConfig("mutex-test.rcS", "128MB")],
"ArmAndroid-GB": [
SysConfig(
"null.rcS",
"256MB",
["ARMv7a-Gingerbread-Android.SMP.mouse.nolock.clean.img"],
None,
"android-gingerbread",
)
],
"bbench-gb": [
SysConfig(
"bbench-gb.rcS",
"256MB",
["ARMv7a-Gingerbread-Android.SMP.mouse.nolock.img"],
None,
"android-gingerbread",
)
],
"ArmAndroid-ICS": [
SysConfig(
"null.rcS",
"256MB",
["ARMv7a-ICS-Android.SMP.nolock.clean.img"],
None,
"android-ics",
)
],
"bbench-ics": [
SysConfig(
"bbench-ics.rcS",
"256MB",
["ARMv7a-ICS-Android.SMP.nolock.img"],
None,
"android-ics",
)
],
}

benchs = list(Benchmarks.keys())
Expand Down
96 changes: 60 additions & 36 deletions configs/common/CacheConfig.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -45,30 +45,33 @@
from common.Caches import *
from common import ObjectList


def _get_hwp(hwp_option):
if hwp_option == None:
return NULL

hwpClass = ObjectList.hwp_list.get(hwp_option)
return hwpClass()


def _get_cache_opts(level, options):
opts = {}

size_attr = '{}_size'.format(level)
size_attr = "{}_size".format(level)
if hasattr(options, size_attr):
opts['size'] = getattr(options, size_attr)
opts["size"] = getattr(options, size_attr)

assoc_attr = '{}_assoc'.format(level)
assoc_attr = "{}_assoc".format(level)
if hasattr(options, assoc_attr):
opts['assoc'] = getattr(options, assoc_attr)
opts["assoc"] = getattr(options, assoc_attr)

prefetcher_attr = '{}_hwp_type'.format(level)
prefetcher_attr = "{}_hwp_type".format(level)
if hasattr(options, prefetcher_attr):
opts['prefetcher'] = _get_hwp(getattr(options, prefetcher_attr))
opts["prefetcher"] = _get_hwp(getattr(options, prefetcher_attr))

return opts


def config_cache(options, system):
if options.external_memory_system and (options.caches or options.l2cache):
print("External caches and internal caches are exclusive options.\n")
Expand All @@ -84,24 +87,34 @@ def config_cache(options, system):
print("O3_ARM_v7a_3 is unavailable. Did you compile the O3 model?")
sys.exit(1)

dcache_class, icache_class, l2_cache_class, walk_cache_class = \
core.O3_ARM_v7a_DCache, core.O3_ARM_v7a_ICache, \
core.O3_ARM_v7aL2, \
None
dcache_class, icache_class, l2_cache_class, walk_cache_class = (
core.O3_ARM_v7a_DCache,
core.O3_ARM_v7a_ICache,
core.O3_ARM_v7aL2,
None,
)
elif options.cpu_type == "HPI":
try:
import cores.arm.HPI as core
except:
print("HPI is unavailable.")
sys.exit(1)

dcache_class, icache_class, l2_cache_class, walk_cache_class = \
core.HPI_DCache, core.HPI_ICache, core.HPI_L2, None
dcache_class, icache_class, l2_cache_class, walk_cache_class = (
core.HPI_DCache,
core.HPI_ICache,
core.HPI_L2,
None,
)
else:
dcache_class, icache_class, l2_cache_class, walk_cache_class = \
L1_DCache, L1_ICache, L2Cache, None

if buildEnv['TARGET_ISA'] in ['x86', 'riscv']:
dcache_class, icache_class, l2_cache_class, walk_cache_class = (
L1_DCache,
L1_ICache,
L2Cache,
None,
)

if buildEnv["TARGET_ISA"] in ["x86", "riscv"]:
walk_cache_class = PageTableWalkerCache

# Set the cache line size of the system
Expand All @@ -118,10 +131,11 @@ def config_cache(options, system):
# Provide a clock for the L2 and the L1-to-L2 bus here as they
# are not connected using addTwoLevelCacheHierarchy. Use the
# same clock as the CPUs.
system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
**_get_cache_opts('l2', options))
system.l2 = l2_cache_class(
clk_domain=system.cpu_clk_domain, **_get_cache_opts("l2", options)
)

system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
system.tol2bus = L2XBar(clk_domain=system.cpu_clk_domain)
system.l2.cpu_side = system.tol2bus.mem_side_ports
system.l2.mem_side = system.membus.cpu_side_ports

Expand All @@ -130,8 +144,8 @@ def config_cache(options, system):

for i in range(options.num_cpus):
if options.caches:
icache = icache_class(**_get_cache_opts('l1i', options))
dcache = dcache_class(**_get_cache_opts('l1d', options))
icache = icache_class(**_get_cache_opts("l1i", options))
dcache = dcache_class(**_get_cache_opts("l1d", options))

# If we have a walker cache specified, instantiate two
# instances here
Expand Down Expand Up @@ -159,8 +173,9 @@ def config_cache(options, system):

# When connecting the caches, the clock is also inherited
# from the CPU in question
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
iwalkcache, dwalkcache)
system.cpu[i].addPrivateSplitL1Caches(
icache, dcache, iwalkcache, dwalkcache
)

if options.memchecker:
# The mem_side ports of the caches haven't been connected yet.
Expand All @@ -174,47 +189,56 @@ def config_cache(options, system):
# on these names. For simplicity, we would advise configuring
# it to use this naming scheme; if this isn't possible, change
# the names below.
if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
if buildEnv["TARGET_ISA"] in ["x86", "arm", "riscv"]:
system.cpu[i].addPrivateSplitL1Caches(
ExternalCache("cpu%d.icache" % i),
ExternalCache("cpu%d.dcache" % i),
ExternalCache("cpu%d.itb_walker_cache" % i),
ExternalCache("cpu%d.dtb_walker_cache" % i))
ExternalCache("cpu%d.icache" % i),
ExternalCache("cpu%d.dcache" % i),
ExternalCache("cpu%d.itb_walker_cache" % i),
ExternalCache("cpu%d.dtb_walker_cache" % i),
)
else:
system.cpu[i].addPrivateSplitL1Caches(
ExternalCache("cpu%d.icache" % i),
ExternalCache("cpu%d.dcache" % i))
ExternalCache("cpu%d.icache" % i),
ExternalCache("cpu%d.dcache" % i),
)

system.cpu[i].createInterruptController()
if options.l2cache:
system.cpu[i].connectAllPorts(
system.tol2bus.cpu_side_ports,
system.membus.cpu_side_ports, system.membus.mem_side_ports)
system.membus.cpu_side_ports,
system.membus.mem_side_ports,
)
elif options.external_memory_system:
system.cpu[i].connectUncachedPorts(
system.membus.cpu_side_ports, system.membus.mem_side_ports)
system.membus.cpu_side_ports, system.membus.mem_side_ports
)
else:
system.cpu[i].connectBus(system.membus)

return system


# ExternalSlave provides a "port", but when that port connects to a cache,
# the connecting CPU SimObject wants to refer to its "cpu_side".
# The 'ExternalCache' class provides this adaptation by rewriting the name,
# eliminating distracting changes elsewhere in the config code.
class ExternalCache(ExternalSlave):
def __getattr__(cls, attr):
if (attr == "cpu_side"):
if attr == "cpu_side":
attr = "port"
return super(ExternalSlave, cls).__getattr__(attr)

def __setattr__(cls, attr, value):
if (attr == "cpu_side"):
if attr == "cpu_side":
attr = "port"
return super(ExternalSlave, cls).__setattr__(attr, value)


def ExternalCacheFactory(port_type):
def make(name):
return ExternalCache(port_data=name, port_type=port_type,
addr_ranges=[AllMemory])
return ExternalCache(
port_data=name, port_type=port_type, addr_ranges=[AllMemory]
)

return make
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