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Resolve the warning when running the project #4

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Resolve the warning when running the project #4

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8 changes: 2 additions & 6 deletions src/main/scala/riscv/core/ALUControl.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -19,9 +19,7 @@ class ALUControl extends Module {

switch(io.opcode) {
is(InstructionTypes.I) {
io.alu_funct := MuxLookup(
io.funct3,
ALUFunctions.zero,
io.alu_funct := MuxLookup(io.funct3, ALUFunctions.zero)(
IndexedSeq(
InstructionsTypeI.addi -> ALUFunctions.add,
InstructionsTypeI.slli -> ALUFunctions.sll,
Expand All @@ -35,9 +33,7 @@ class ALUControl extends Module {
)
}
is(InstructionTypes.RM) {
io.alu_funct := MuxLookup(
io.funct3,
ALUFunctions.zero,
io.alu_funct := MuxLookup(io.funct3, ALUFunctions.zero)(
IndexedSeq(
InstructionsTypeR.add_sub -> Mux(io.funct7(5), ALUFunctions.sub, ALUFunctions.add),
InstructionsTypeR.sll -> ALUFunctions.sll,
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4 changes: 1 addition & 3 deletions src/main/scala/riscv/core/Execute.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -43,9 +43,7 @@ class Execute extends Module {
io.mem_alu_result := alu.io.result
io.if_jump_flag := opcode === Instructions.jal ||
(opcode === Instructions.jalr) ||
(opcode === InstructionTypes.B) && MuxLookup(
funct3,
false.B,
(opcode === InstructionTypes.B) && MuxLookup(funct3, false.B)(
IndexedSeq(
InstructionsTypeB.beq -> (io.reg1_data === io.reg2_data),
InstructionsTypeB.bne -> (io.reg1_data =/= io.reg2_data),
Expand Down
4 changes: 1 addition & 3 deletions src/main/scala/riscv/core/InstructionDecode.scala
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Expand Up @@ -147,9 +147,7 @@ class InstructionDecode extends Module {

io.regs_reg1_read_address := Mux(opcode === Instructions.lui, 0.U(Parameters.PhysicalRegisterAddrWidth), rs1)
io.regs_reg2_read_address := rs2
val immediate = MuxLookup(
opcode,
Cat(Fill(20, io.instruction(31)), io.instruction(31, 20)),
val immediate = MuxLookup(opcode, Cat(Fill(20, io.instruction(31)), io.instruction(31, 20)))(
IndexedSeq(
InstructionTypes.I -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
InstructionTypes.L -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
Expand Down
12 changes: 3 additions & 9 deletions src/main/scala/riscv/core/MemoryAccess.scala
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Expand Up @@ -30,22 +30,16 @@ class MemoryAccess extends Module {

when(io.memory_read_enable) {
val data = io.memory_bundle.read_data
io.wb_memory_read_data := MuxLookup(
io.funct3,
0.U,
io.wb_memory_read_data := MuxLookup(io.funct3, 0.U)(
IndexedSeq(
InstructionsTypeL.lb -> MuxLookup(
mem_address_index,
Cat(Fill(24, data(31)), data(31, 24)),
InstructionsTypeL.lb -> MuxLookup(mem_address_index, Cat(Fill(24, data(31)), data(31, 24)))(
IndexedSeq(
0.U -> Cat(Fill(24, data(7)), data(7, 0)),
1.U -> Cat(Fill(24, data(15)), data(15, 8)),
2.U -> Cat(Fill(24, data(23)), data(23, 16))
)
),
InstructionsTypeL.lbu -> MuxLookup(
mem_address_index,
Cat(Fill(24, 0.U), data(31, 24)),
InstructionsTypeL.lbu -> MuxLookup(mem_address_index, Cat(Fill(24, 0.U), data(31, 24)))(
IndexedSeq(
0.U -> Cat(Fill(24, 0.U), data(7, 0)),
1.U -> Cat(Fill(24, 0.U), data(15, 8)),
Expand Down
4 changes: 1 addition & 3 deletions src/main/scala/riscv/core/WriteBack.scala
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Expand Up @@ -15,9 +15,7 @@ class WriteBack extends Module {
val regs_write_source = Input(UInt(2.W))
val regs_write_data = Output(UInt(Parameters.DataWidth))
})
io.regs_write_data := MuxLookup(
io.regs_write_source,
io.alu_result,
io.regs_write_data := MuxLookup(io.regs_write_source, io.alu_result)(
IndexedSeq(
RegWriteSource.Memory -> io.memory_read_data,
RegWriteSource.NextInstructionAddress -> (io.instruction_address + 4.U)
Expand Down