Add 'Offered Resources', update telegram link, changes for test portal

README.md

@@ -216,9 +216,29 @@ AWS online documentation:
   * Shell Interface: <https://github.com/aws/aws-fpga/blob/master/hdk/docs/AWS_Shell_Interface_Specification.md>
   * Simulating CL Designs: <https://github.com/aws/aws-fpga/blob/master/hdk/docs/RTL_Simulating_CL_Designs.md>
 
+## Offered Resources
+
+**Xilinx Vivado Trial License**
+
+Xilinx has offered to provide contestants with a trial license of Vivado for use in the competition. If you would like to receive an extended trial license please complete an contest entry form and provide the host name and the MAC address of the computer on which you will install the trial license. This information can be e-mailed to [email protected]
+
+**AWS Promotional Credits**
+
+AWS has offered to provide a limited number of promotional credits to contestants who wish to test their designs directly on the AWS F1 infrastructure. To receive promotional credits for testing please complete an entry form, share your preliminary contest entry GitHub with the account "simonatsn", and provide the following information:
+
+First Name:
+Last Name:
+Email:
+AWS Account ID:
+Occupation/ Role:
+Company/ Organization (if applicable):
+Website (if applicable):
+
+The above information can be e-mailed to [email protected]. The GitHub repository that is shared must contain non-trivial changes to the baseline repository and will be open-sourced at the completion of the contest.
+
 ## Questions?
 
 Please reach out with any questions, comments, or feedback through any of the following channels:
 - Message Board: https://vdfalliance.discourse.group/
-- Telegram: https://t.me/joinchat/FoVncxdnEPRGRvkt1OuQmQ
+- Telegram: [vdfalliance.org](vdfalliance.org/telegram)
 - E-mail: [email protected]

msu/Makefile

@@ -24,25 +24,7 @@ all: hw_emu
 # Requires verilator
 regress: sim hw_emu_simple judge
 
-judge:
-	$(MAKE) clean
-
-	@echo ""
-	@echo "############################################################"
-	@echo "# Running hardware emulation..."
-	@echo "############################################################"
-	OBJ=obj_hw_emu MOD_LEN=1024 SIMPLE_SQ=0 $(MAKE) hw_emu
-
-	@echo ""
-	@echo "############################################################"
-	@echo "# Synthesizing..."
-	@echo "############################################################"
-	OBJ=obj_hw     MOD_LEN=1024 SIMPLE_SQ=0 $(MAKE) hw
-
-
-hw_emu:
-	make clean
-	OBJ=obj_hw_emu MOD_LEN=1024 SIMPLE_SQ=0 $(MAKE) -C $(SDACCEL_DIR) hw_emu
+judge: synthesis
 
 hw_emu_simple:
 	make clean
@@ -51,10 +33,35 @@ hw_emu_simple:
 hw:
 	MOD_LEN=1024 SIMPLE_SQ=0 $(MAKE) -C $(SDACCEL_DIR) hw
 
+
+# This target is used by the test portal to perform hardware emulation
+hw_emu:
+	make clean
+
+	@echo ""
+	@echo "############################################################"
+	@echo "# Running hardware emulation..."
+	@echo "############################################################"
+	OBJ=obj_hw_emu MOD_LEN=1024 SIMPLE_SQ=0 \
+		$(MAKE) -C $(SDACCEL_DIR) hw_emu |& tee hw_emu.log
+
+# This target is used by the test portal to perform synthesis
 synthesis:
 	make clean
-	OBJ=obj_hw_emu MOD_LEN=1024 SIMPLE_SQ=0 $(MAKE) -C $(SDACCEL_DIR) hw_emu
-	OBJ=obj_hw     MOD_LEN=1024 SIMPLE_SQ=0 $(MAKE) -C $(SDACCEL_DIR) hw
+
+	@echo ""
+	@echo "############################################################"
+	@echo "# Running hardware emulation..."
+	@echo "############################################################"
+	OBJ=obj_hw_emu MOD_LEN=1024 SIMPLE_SQ=0 \
+		$(MAKE) -C $(SDACCEL_DIR) hw_emu |& tee hw_emu.log
+
+	@echo ""
+	@echo "############################################################"
+	@echo "# Synthesizing..."
+	@echo "############################################################"
+	OBJ=obj_hw     MOD_LEN=1024 SIMPLE_SQ=0 \
+		$(MAKE) -C $(SDACCEL_DIR) hw     |& tee hw.log
 
 
 # Additional, mostly verilator, targets

msu/rtl/sdaccel/Makefile.sdaccel

@@ -101,7 +101,7 @@ XCLBIN            := ./xclbin
 include ../utils.mk
 
 DSA               := $(call device2sandsa, $(DEVICE))
-BUILD_DIR         := ./vdf_9cc/_x.$(TARGET).$(DSA)
+BUILD_DIR         := ./vdf/_x.$(TARGET).$(DSA)
 
 CXX               := $(XILINX_SDX)/bin/xcpp
 XOCC              := $(XILINX_SDX)/bin/xocc